11.1 A Scalable Heterogeneous Integrated Two-Stage Vertical Power-Delivery Architecture for High-Performance Computing

Emerging high-performance computing needs in data center, autonomous vehicle, and mobile device processors demand increasingly large peak currents at scaled-CMOS-compatible voltages (

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Bibliographic Details
Main Authors: Hardy, Casey, Pham, Hieu, Jatlaoui, Mohamed Mehdi, Voiron, Frederic, Xie, Tianshi, Chen, Po-Han, Jha, Saket, Mercier, Patrick, Le, Hanh-Phuc
Format: Conference Proceeding
Language:English
Subjects:
High performance computing
Mobile handsets
Multichip modules
Program processors
Rails
Regulators
Thermal conductivity
Online Access:Request full text
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Description
Summary:Emerging high-performance computing needs in data center, autonomous vehicle, and mobile device processors demand increasingly large peak currents at scaled-CMOS-compatible voltages (
ISSN:2376-8606
DOI:10.1109/ISSCC42615.2023.10067315