An HDL Simulator with Direct Register Access for Improving Code Coverage

• Main Authors: Isawa, Ryoichi, Kanaya, Nobuyuki, Fujiwara, Yoshitada, Takehisa, Tatsuya, Ushimaru, Hayato, Arisue, Dai, Makita, Daisuke, Mimura, Satoshi, Inoue, Daisuke
• Format: Conference Proceeding
• Language: English
• Subjects: branch coverage; Codes; Computer bugs; Debugging; Information security; Intellectual property; Measurement; simulation; SMT solver; Verilog; Writing
• ISSN: 2765-9712
• DOI: 10.1109/AsiaJCIS57030.2022.00018

When debugging a DUT (Device Under Test) written in HDL (Hardware Description Language) code in simulation, code coverage is one of the most important evaluation metrics because it indicates how many unchecked statements remain where bugs could be hidden. A typical random test-pattern generator can be used very easily for debugging; however, it could fail to obtain enough code coverage of DUTs because it does not provide effective strategies for code coverage. In this paper, we propose an HDL simulator to improve branch coverage of DUTs up to 100%. A key idea behind our simulator is to directly write values to registers of DUTs for intentionally transfer a state to an unchecked state in the state machine of DUTs. This improves code coverage by executing statements corresponding to an unchecked state. Our simulator uses an SMT (Satisfiability Modulo Theories) solver to obtain the values written to registers from the condition (e.g., if and case) corresponding to an unchecked state. With the evaluation, we confirmed that our simulator successfully obtained a branch coverage of 100% for each of three open-sourced IP (Intellectual Property) core modules. As a bench mark, we also used a random test-pattern generator for those modules.