Test Circuit Design for Accurately Characterizing Cells' Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications

Computing-in-memory (CIM) is a promising technique for energy-efficiently conducting the massive amount of required multiply-and-accumulate (MAC) calculations in neural networks (NNs). The read-decoupled 8T (RD8T) SRAM cell is popular in the CIM designs because of being read disturbance free. Howeve...

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Bibliographic Details
Main Authors: Hong, Hao-Chiao, Lin, Long-Yi, Chen, Bo-Chang
Format: Conference Proceeding
Language:English
Subjects:
characterization
CIM
Circuit synthesis
current
Energy efficiency
Fabrication
Graphical models
Nonvolatile memory
Phase change random access memory
RD8T
SRAM
SRAM cells
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Summary:Computing-in-memory (CIM) is a promising technique for energy-efficiently conducting the massive amount of required multiply-and-accumulate (MAC) calculations in neural networks (NNs). The read-decoupled 8T (RD8T) SRAM cell is popular in the CIM designs because of being read disturbance free. However, local process variations may lead significant errors to the CIM results. This work proposes an accurate on-chip test circuit design for characterizing the output current of every RD8T SRAM cell in a 8-kb RD8T SRAM array fabricated in 90nm CMOS. The experimental results show the detailed and accurate spatial distribution of the RD8T cells which helps optimize the CIM circuit design.
ISSN:2158-1029
DOI:10.1109/ICMTS55420.2023.10094078