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Discrete current limiting circuit for emerging memory programming
This work presents a novel, discrete-component circuit for the electrical characterisation of Resistive Random Access Memory (RRAM). The forming of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transi...
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creator | Laborie, Lao Trotti, Paola Veyret, Killian Cagli, Carlo |
description | This work presents a novel, discrete-component circuit for the electrical characterisation of Resistive Random Access Memory (RRAM). The forming of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transistor. The presented DCL circuit is furthermore benchmarked versus other discrete and integrated typologies, showing dramatic improvement over existing discrete solutions, and comparable performances with integrated architectures. Finally, multi-bit storage is experimentally demonstrated through modulation of the programming current amplitude. |
doi_str_mv | 10.1109/ICMTS55420.2023.10094099 |
format | conference_proceeding |
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The forming of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transistor. The presented DCL circuit is furthermore benchmarked versus other discrete and integrated typologies, showing dramatic improvement over existing discrete solutions, and comparable performances with integrated architectures. Finally, multi-bit storage is experimentally demonstrated through modulation of the programming current amplitude.</description><subject>Computer architecture</subject><subject>current overshoot</subject><subject>DCL</subject><subject>discrete current limiting circuit</subject><subject>Limiting</subject><subject>memory programming</subject><subject>Microprocessors</subject><subject>Modulation</subject><subject>parasitic capacitance</subject><subject>Programming</subject><subject>Resistive RAM</subject><subject>Resistors</subject><subject>RRAM</subject><subject>test structure</subject><issn>2158-1029</issn><isbn>9798350346534</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2023</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1j8tOwzAQAA0SEqX0Dzj4BxJ2vd4kPlbh0UpFHCjnKrGdYFQ3lZMe-veAgNNIcxhphJAIOSKY-3X9sn1j1gpyBYpyBDAajLkQC1OaihhIF0z6UswUcpUhKHMtbsbxE0ABMs7E8iGMNvnJS3tKyR8muQ8xTOHQSxuSPYVJdkOSPvrU_8jo45DO8piGPjUxfqtbcdU1-9Ev_jgX70-P23qVbV6f1_Vyk30g05QZhciNKV3hrGsMt6UunCLiwhcVtpVx2tvWkVWGC6LSgi25A9chaHCupbm4--0G7_3umEJs0nn3v0xfmd9MXQ</recordid><startdate>20230327</startdate><enddate>20230327</enddate><creator>Laborie, Lao</creator><creator>Trotti, Paola</creator><creator>Veyret, Killian</creator><creator>Cagli, Carlo</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20230327</creationdate><title>Discrete current limiting circuit for emerging memory programming</title><author>Laborie, Lao ; Trotti, Paola ; Veyret, Killian ; Cagli, Carlo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-h153t-92115a97d6dcda95b746d23356e681b89d4ecbd3c2956337c0c75f0df1040ddb3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Computer architecture</topic><topic>current overshoot</topic><topic>DCL</topic><topic>discrete current limiting circuit</topic><topic>Limiting</topic><topic>memory programming</topic><topic>Microprocessors</topic><topic>Modulation</topic><topic>parasitic capacitance</topic><topic>Programming</topic><topic>Resistive RAM</topic><topic>Resistors</topic><topic>RRAM</topic><topic>test structure</topic><toplevel>online_resources</toplevel><creatorcontrib>Laborie, Lao</creatorcontrib><creatorcontrib>Trotti, Paola</creatorcontrib><creatorcontrib>Veyret, Killian</creatorcontrib><creatorcontrib>Cagli, Carlo</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Laborie, Lao</au><au>Trotti, Paola</au><au>Veyret, Killian</au><au>Cagli, Carlo</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Discrete current limiting circuit for emerging memory programming</atitle><btitle>2023 35th International Conference on Microelectronic Test Structure (ICMTS)</btitle><stitle>ICMTS</stitle><date>2023-03-27</date><risdate>2023</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><eissn>2158-1029</eissn><eisbn>9798350346534</eisbn><abstract>This work presents a novel, discrete-component circuit for the electrical characterisation of Resistive Random Access Memory (RRAM). The forming of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transistor. The presented DCL circuit is furthermore benchmarked versus other discrete and integrated typologies, showing dramatic improvement over existing discrete solutions, and comparable performances with integrated architectures. Finally, multi-bit storage is experimentally demonstrated through modulation of the programming current amplitude.</abstract><pub>IEEE</pub><doi>10.1109/ICMTS55420.2023.10094099</doi><tpages>4</tpages></addata></record> |
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language | eng |
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source | IEEE Xplore All Conference Series |
subjects | Computer architecture current overshoot DCL discrete current limiting circuit Limiting memory programming Microprocessors Modulation parasitic capacitance Programming Resistive RAM Resistors RRAM test structure |
title | Discrete current limiting circuit for emerging memory programming |
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