A high-speed image acquisition system based on state machine and fast ADCs

The present work reports on the development of a digital system for image acquisition which is able to process two electric signals of amplitude varying between 0 and 10 V. The system correlates both signals in a two-dimensional histogram. X and Y coordinates for every event are derived from the amp...

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Bibliographic Details
Main Authors: Lima, H.P., Barbosa, A.F., Guedes, G.P., Farias, P.C.M.A., de Andrade Filho, L.M.
Format: Conference Proceeding
Language:English
Subjects:
Analog-digital conversion
Data acquisition
Digital systems
Hardware
Histograms
Instruction sets
Microcomputers
Random access memory
Signal processing
SRAM chips
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Summary:The present work reports on the development of a digital system for image acquisition which is able to process two electric signals of amplitude varying between 0 and 10 V. The system correlates both signals in a two-dimensional histogram. X and Y coordinates for every event are derived from the amplitudes of the two coincident signals. The hardware basically consists of two analog-to-digital converters (ADCs), control electronics, and one 1M Static Random Access Memory (SRAM), implemented in a card that is plugged into any personal computer with an ISA bus. The data acquisition rate may be as high as 1.0 /spl times/ 10/sup 6/ events per second, and does not depend on the PC processor. The software code has been written in the Delphi environment using assembly routines. Image sizes may be chosen from 128 /spl times/ 128 to 1024 /spl times/ 1024 pixels and may be viewed in three-dimensional graphics. Images are shown to illustrate the applicability to two-dimensional position sensitive X-ray detectors.
ISSN:1082-3654
2577-0829
DOI:10.1109/NSSMIC.2001.1009652