Reconfiguration technique for reducing test time and test data volume in Illinois Scan Architecture based designs

As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) manufacturing cost. This paper addresses the issue of decreasing test cost by lowering the test data bits and...

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Bibliographic Details
Main Authors: Pandey, A.R., Patel, J.H.
Format: Conference Proceeding
Language:English
Subjects:
Automatic test pattern generation
Circuit testing
Clocks
Computer architecture
Costs
Hardware
Integrated circuit manufacture
Integrated circuit testing
Semiconductor device testing
Very large scale integration
Online Access:Request full text
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Summary:As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) manufacturing cost. This paper addresses the issue of decreasing test cost by lowering the test data bits and the number of clock cycles required to test a chip. We propose a technique based on the reconfiguration of scan chains to reduce test time and test data volume for Illinois Scan Architecture (ILS) based designs. This technique is presented with details of hardware implementation as well as the test generation and test application procedures. The reduction in test time and test data volume achieved using this technique is quite significant in most circuits.
DOI:10.1109/VTS.2002.1011104