Influence of Back Gate Bias on the Hot Carrier Reliability of DSOI nMOSFET

The hot carrier reliability under different back-gate bias in DSOI nMOSFET is studied. Reverse back-gate bias results in an over-all larger time exponents than the forward back-gate bias, which is attributed to the increased lateral electric field (as supported by TCAD simulation) and consequently a...

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Bibliographic Details
Main Authors: Zhang, Xinyi, Wang, Kewei, Wang, Fang, Li, Jiangjiang, Wu, Zhicheng, Li, Duoli, Li, Bo, Bu, Jianhui, Han, Zhengsheng
Format: Conference Proceeding
Language:English
Subjects:
back gate bias
Degradation
DSOI
hot carrier reliability
Hot carriers
hot electron induced punch-through effect (HEIP)
Interface states
Logic gates
MOSFET circuits
Simulation
Threshold voltage
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Summary:The hot carrier reliability under different back-gate bias in DSOI nMOSFET is studied. Reverse back-gate bias results in an over-all larger time exponents than the forward back-gate bias, which is attributed to the increased lateral electric field (as supported by TCAD simulation) and consequently a stronger interface state generation (related to SVE mechanisms). Such strong time acceleration is crucial for long term reliability prediction under circuit operation. The abnormal deviation among threshold voltage shift, linear/saturation drain current degradation is observed: through careful inspection of the degradation of the I- V characteristics, the competing role of the interface state generation and hot hole trapping is revealed, with a virtual channel shortening effect as supported by the increased DIBL values.
ISSN:1938-1891
DOI:10.1109/IRPS48203.2023.10117718