Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Pow...

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Bibliographic Details
Main Authors: Xuejue Huang, Restle, P., Bucelot, T., Yu Cao, Tsu-Jae King
Format: Conference Proceeding
Language:English
Subjects:
Analytical models
Applied sciences
Circuit simulation
Clocks
Delay
Design optimization
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Frequency locked loops
Inductance
Integrated circuit interconnections
Integrated circuits
Proximity effect
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Solid modeling
Online Access:Request full text
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Description
Summary:An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.
DOI:10.1109/CICC.2002.1012758