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HFGCN: High-speed and Fully-optimized GCN Accelerator
graph convolutional network (GCN) is a type of neural network that inference new nodes based on the connectivity of the graphs. GCN requires high-calculation volume for processing, similar to other neural networks requiring significant calculation. In this paper, we propose a new hardware architectu...
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| creator | Han, MinSeok Kim, Jiwan Kim, Donggeon Jeong, Hyunuk Jung, Gilho Oh, Myeongwon Lee, Hyundong Go, Yunjeong Kim, HyunWoo Kim, Jongbeom Song, Taigon |
| description | graph convolutional network (GCN) is a type of neural network that inference new nodes based on the connectivity of the graphs. GCN requires high-calculation volume for processing, similar to other neural networks requiring significant calculation. In this paper, we propose a new hardware architecture for GCN that tackles the problem of wasted cycles during processing. We propose a new scheduler module that reduces memory access through aggregation and an optimized systolic array with improved delay. We compare our study with the state-of-the-art GCN accelerator and show outperforming results. |
| doi_str_mv | 10.1109/ISQED57927.2023.10129340 |
| format | conference_proceeding |
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GCN requires high-calculation volume for processing, similar to other neural networks requiring significant calculation. In this paper, we propose a new hardware architecture for GCN that tackles the problem of wasted cycles during processing. We propose a new scheduler module that reduces memory access through aggregation and an optimized systolic array with improved delay. We compare our study with the state-of-the-art GCN accelerator and show outperforming results.</abstract><pub>IEEE</pub><doi>10.1109/ISQED57927.2023.10129340</doi><tpages>7</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | EISSN: 1948-3295 |
| ispartof | 2023 24th International Symposium on Quality Electronic Design (ISQED), 2023, p.1-7 |
| issn | 1948-3295 |
| language | eng |
| recordid | cdi_ieee_primary_10129340 |
| source | IEEE Xplore All Conference Series |
| subjects | Convolution Decoding Delays Hardware Neural networks Process control Systolic arrays |
| title | HFGCN: High-speed and Fully-optimized GCN Accelerator |
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