Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory

A vast number of data used for Artificial intelligence causes bottleneck between the processor and memory. To tackle this issue, a technology that embeds a processing unit in the memory (PIM: Processing-in Memory) has been proposed. However, SRAM/DRAM based PIM have a issue for lack of capacity. Thu...

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Bibliographic Details
Main Authors: Kim, Hyunwoo, Lee, Hyundong, Kim, Jongbeom, Go, Yunjeong, Baek, Seungwon, Song, Jaehong, Kim, Junhyeon, Jung, Minyoung, Kim, Hyodong, Kim, Seongju, Song, Taigon
Format: Conference Proceeding
Language:English
Subjects:
Arrays
Artificial intelligence
Computer architecture
deep neural network
Flash memories
Microprocessors
NAND Flash memory
near-Memory processing
Random access memory
Registers
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Summary:A vast number of data used for Artificial intelligence causes bottleneck between the processor and memory. To tackle this issue, a technology that embeds a processing unit in the memory (PIM: Processing-in Memory) has been proposed. However, SRAM/DRAM based PIM have a issue for lack of capacity. Thus, we propose a NAND flash PIM scheme that shares the cache register. Our scheme significantly reduces the read latency and operation time by -22.8% and -43.7%, compared to the conventional memory system. The power-performance-area (PPA) was reduced by 17.2% by shortening the number of cycles. Our NAND PIM specializes in tasks requiring high-performance computing.
ISSN:1948-3295
DOI:10.1109/ISQED57927.2023.10129383