A combined N/PFET CFET based design and logic technology framework for CMOS applications

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2023-12, Vol.42 (12), p.1-1
• Main Authors: Zhu, Xiaona, Ding, Rongzheng, Tao, Ouwen, Zhao, Yage, Tang, Peishun, Zhang, David Wei, Lu, Ye, Yu, Shaofeng
• Format: Article
• Language: English
• Subjects: Circuit design; CMOS; Compact model; Complementary field-effect transistor (CFET); Computer architecture; Field effect transistors; Integrated circuit modeling; Inverters; Logic design; Logic gates; Microprocessors; Neural networks; New technology; Random access memory; Semiconductor devices; standard cell library; Transistors
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2023.3282576

We propose a new technology and design platform using combined common gate N/PFET CFET as basic element for CMOS circuit applications. Two CFET unit structures, namely common gate (CG) and N-gate (NG), are identified to form base design elements. Through the two units, all circuit logic functions in standard cell library and SRAM can be realized without significant process complication. A Multi-gradient Neural Network (MNN) based SPICE compact modeling methodology is developed for these CFET units. As an example, MNN model generation is illustrated for CG with the output matching well with the TCAD data within and beyond the range of model extraction. Circuit simulations are exercised using the MNN models and demonstrated successfully the expected circuit functionalities. As the CFET technology be adopted as mainstream in future, this novel design framework proposed would enable efficient logic design.