Impact of Gate Morphology on Electrical Performances of Recessed GaN-on Si MOS channel-HEMT for Different Channel Orientations

• Main Authors: Piotrowic, C., Mohamad, B., Rocha, P. Fernandes Paes Pinto, Malbert, N., Ruel, S., Pimenta-Barros, P., Jaud, M.-A., Vauche, L., Royer, C. Le
• Format: Conference Proceeding
• Language: English
• Subjects: GaN; HEMT; Logic gates; measurements; mobility; Morphology; numerical simulation; ON state resistance; Performance evaluation; recessed gate; Resistance; Semiconductor device measurement; Silicon; Threshold voltage
• ISSN: 1946-0201
• DOI: 10.1109/ISPSD57135.2023.10147642

In this paper, we study the effect of the gate morphology and the impact of the crystallographic channel orientation on the on-state electrical performances of the GaN-on-Si MOS-HEMTs with a fully recessed gate. By combining physical and chemical characterizations (TEM, EDX, and AFM), experimental measurements and TCAD simulations, the effect of dry-etching and wet cleaning on the gate morphology and their consequences on electrical performances are studied. Moreover, an anisotropy behavior with the Atomic Layer Etching (ALE) and wet processes between (11\overline{2}0) and (1\overline{1}00) planes is highlighted. Using the new partitioning methodology, the contributions of the bottom and sidewall regions are evaluated separately in terms of resistance and mobility. The good agreement between TCAD simulations and experimental I_{D}(V_{G} ) characteristics validates the methodology and highlights the gate morphology importance for the device's on-state performances in terms of resistance, mobility, threshold voltage and subthreshold slope.