Isolated JFET Design and Performance Analyze by Experiment Based on Standard 0.18µm BCD Platform

This study investigates design of two kinds of JFET by experiment based on a standard 0.18µm BCD platform, satisfying the 60V on-state application. Meanwhile a range of pinch-off voltage (VP) from -IV to −6V is achieved and off-state breakdown voltage (BVoFF) reaches 107V even extending to 117V. By...

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Bibliographic Details
Main Authors: Ma, Dingxiang, Gao, Yue, Hou, Dican, Yuan, Zhangyi'an, Qiao, Ming, Zhen, Shaowei, Zhang, Bo
Format: Conference Proceeding
Language:English
Subjects:
DIBL
Fluctuations
JFET
JFETs
pinch-off voltage
Power measurement
process fluctuation
Semiconductor device measurement
Stability analysis
standard BCD platform
Voltage fluctuations
Voltage measurement
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Summary:This study investigates design of two kinds of JFET by experiment based on a standard 0.18µm BCD platform, satisfying the 60V on-state application. Meanwhile a range of pinch-off voltage (VP) from -IV to −6V is achieved and off-state breakdown voltage (BVoFF) reaches 107V even extending to 117V. By utilizing the P-type buried layer (PBL), maximum output current fabricated realizes 1.45mA without sacrificing BVoFF and VP. What's more, drain induced barrier lowering (DIBL) effect is analyzed with different applied voltages. Considering yield, BV OFF and V p of both structures are measured from different dies to illustrate its stability of layout design.
ISSN:1946-0201
DOI:10.1109/ISPSD57135.2023.10147671