A Fully-Reflective Wi-Fi-Compatible Backscatter Communication System With Retro-Reflective MIMO Gain for Improved Range

This article presents an integrated circuit (IC) designed to enable low-power long-range backscatter communication with commodity Wi-Fi transceivers. The proposed chip endeavors to improve the most critical and difficult specification in Wi-Fi backscatter systems: range. It does so through two propo...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2023-09, Vol.58 (9), p.1-12
Main Authors: Meng, Miao, Dunna, Manideep, Kuo, Shih-Kai, Yu, Hans Chinghan, Wang, Po-Han Peter, Bharadia, Dinesh, Mercier, Patrick P.
Format: Article
Language:English
Subjects:
Amplitude modulation
Backscatter
Backscatter communication
Backscattering
Circuit design
Communications systems
Integrated circuits
Internet-of-Things (IoT)
low-power wireless system
MIMO communication
Modulation
Power combiners
Quadrature phase shift keying
Radio frequency
range improvement
Reflectance
Single sideband transmission
Switches
Synchronism
Synchronization
wake-up radios
Wi-Fi
Wireless fidelity
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Summary:This article presents an integrated circuit (IC) designed to enable low-power long-range backscatter communication with commodity Wi-Fi transceivers. The proposed chip endeavors to improve the most critical and difficult specification in Wi-Fi backscatter systems: range. It does so through two proposed techniques: 1) a fully-reflective single-antenna backscatter solution, whereby the termination of a power combiner always has a reflection coefficient near 1 to ensure high reflected power while enabling single-sideband (SSB) quadrature phase shift keying (QPSK) modulation with frequency-translation to separate Wi-Fi channel and 2) a retro-reflective multiple-in-multiple-out (MIMO) approach that redirects incident Wi-Fi signals, after SSB QPSK modulation, back to a colocated access point (AP) with MIMO gain. The proposed chip also implemented a counter-based wake-up scheme within a synchronization receiver (RX) to achieve standards-compatible wake-up with high synchronization accuracy. Implemented in 65-nm CMOS, the wake-up RX consumes 4.5 \mu W and achieves a sensitivity of - 43.5 dBm, while the synchronization RX consumes an average power of 4.8 \mu W and achieves a synchronization accuracy of at least 150 ns for input power of - 35 dBm or better. During backscattering, the IC consumes 32 and 38 \mu W and attains an AP-to-tag range of 13 and 23 m for the fully-reflective and retro-reflective MIMO approaches, respectively.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2023.3281553