A 4-bit 4.5ns-Latency Pseudo-ReRAM Computing-In-Memory Macro with Self Error-Correcting DTCbased WL drivers and 6-bit CDAC-less Column ADCs having Ultra-narrow Pitch

This paper presents a 32x32 pseudo-ReRAM-based analog computing-in-memory (CIM) macro in 28nm CMOS. A 4b self-error-correcting word-line (WL) driver reduces the analog compute inaccuracy while minimizing the latency. A stability compensating dummy row maximizes the accumulation length of the multipl...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2023-06, p.1-1
Main Authors: Kim, Jongho, Oh, Young H., Kim, Hyeonsik, Lee, Jae W., Kim, Jintae
Format: Article
Language:English
Subjects:
Capacitors
charge injection SAR (ci-SAR)
Circuit stability
Clamps
Computing-in-memory (CIM)
Delays
digital-to-time converter (DTC)
Microprocessors
multiply-andaccumulate (MAC)
Throughput
Voltage
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Summary:This paper presents a 32x32 pseudo-ReRAM-based analog computing-in-memory (CIM) macro in 28nm CMOS. A 4b self-error-correcting word-line (WL) driver reduces the analog compute inaccuracy while minimizing the latency. A stability compensating dummy row maximizes the accumulation length of the multiply-and-accumulate (MAC). The columnsensing dual-phase 6b successive-approximation-register (SAR) analog-to-digital-converter (ADC) maximizes the through-put with minimized pitch. The proposed CIM occupies an active area of 0.0155mm2 and consumes 4.36mW with an average energy efficiency of 25.8TOPS/W. The measured performance achieves the highest normalized throughput with an end-to-end inference accuracy comparable to FP32 with less than a 0.11% drop.
ISSN:1549-7747
DOI:10.1109/TCSII.2023.3273290