Loading…
An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET
Bayesian neural networks (BNNs) have been proposed to address the problems of overfitting and overconfident decision making, common in conventional neural networks (NNs), due to their ability to model and express uncertainty in their predictions. However, BNNs require multiple inference passes to pr...
Saved in:
Published in: | IEEE journal of solid-state circuits 2023-10, Vol.58 (10), p.1-13 |
---|---|
Main Authors: | , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | cdi_FETCH-LOGICAL-c294t-a66968a8b37177498f73cbdba4cb568e0111a93b0b50080377fc2468b16150da3 |
---|---|
cites | cdi_FETCH-LOGICAL-c294t-a66968a8b37177498f73cbdba4cb568e0111a93b0b50080377fc2468b16150da3 |
container_end_page | 13 |
container_issue | 10 |
container_start_page | 1 |
container_title | IEEE journal of solid-state circuits |
container_volume | 58 |
creator | Dorrance, Richard Dasalukunte, Deepak Wang, Hechen Liu, Renzhi Carlton, Brent |
description | Bayesian neural networks (BNNs) have been proposed to address the problems of overfitting and overconfident decision making, common in conventional neural networks (NNs), due to their ability to model and express uncertainty in their predictions. However, BNNs require multiple inference passes to produce the necessary posterior distributions used to generate these highly desirable uncertainty estimates. As such, BNNs require not only an efficient, high-performance multiply-accumulation (MAC) operation but also an efficient Gaussian random number generator (GRNG) with high-quality statistics. In this article, an NN accelerator chip, leveraging a multi-bit analog compute-in-memory (CiM) static random-access memory (SRAM) macro, with a tightly coupled and highly efficient GRNG scheme, is presented in the Intel 22FFL process. The CiM macro achieves a peak energy efficiency of 32.2 TOP/sW, with 8-bit precision, while ensuring accurate on-chip matrix-vector multiplications (MVMs) with a computation error less than 0.5%. The variable precision GRNG achieves a peak throughput of 7.31 GSamp/s for an energy efficiency of \sim 1 TSamp/J. Overall, our proposed system achieves a peak energy efficiency of 1170 GOP/s/W, a 35-133 \times improvement over the state-of-the-art BNN accelerators, with 98.14% accuracy for the MNIST dataset. |
doi_str_mv | 10.1109/JSSC.2023.3283186 |
format | article |
fullrecord | <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_ieee_primary_10153995</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10153995</ieee_id><sourcerecordid>2869328170</sourcerecordid><originalsourceid>FETCH-LOGICAL-c294t-a66968a8b37177498f73cbdba4cb568e0111a93b0b50080377fc2468b16150da3</originalsourceid><addsrcrecordid>eNpNkM1PAjEQxRujiYj-ASYemnhe7LT70R4R-TKIiUD0tunuzmIVuthdNNz80y2Bg6eXmbz3JvMj5BpYB4Cpu8fZrNfhjIuO4FKAjE9IC6JIBpCIt1PSYgxkoDhj5-Sirj_8GIYSWuS3a2nfolvugn5Zmtygbei93mFttKVT3Dq98tL8VO6TdvMcV-h0Uzn6app32jNPVNuCajo3awzGtkG3Qv2NBR3pQq-1K-iDWZrGlwxfpkO6qI1dUs4Du6YDYwf9-SU5K_WqxqujtsnCb3ujYPI8HPe6kyDnKmwCHccqllpmIoEkCZUsE5FnRabDPItiiQwAtBIZyyLGJBNJUuY8jGUGMUSs0KJNbg-9G1d9bbFu0o9q66w_mXIZK08NEuZdcHDlrqprh2W6cca_sUuBpXvQ6R50ugedHkH7zM0hYxDxnx8ioVQk_gBvWnfG</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2869328170</pqid></control><display><type>article</type><title>An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET</title><source>IEEE Xplore (Online service)</source><creator>Dorrance, Richard ; Dasalukunte, Deepak ; Wang, Hechen ; Liu, Renzhi ; Carlton, Brent</creator><creatorcontrib>Dorrance, Richard ; Dasalukunte, Deepak ; Wang, Hechen ; Liu, Renzhi ; Carlton, Brent</creatorcontrib><description><![CDATA[Bayesian neural networks (BNNs) have been proposed to address the problems of overfitting and overconfident decision making, common in conventional neural networks (NNs), due to their ability to model and express uncertainty in their predictions. However, BNNs require multiple inference passes to produce the necessary posterior distributions used to generate these highly desirable uncertainty estimates. As such, BNNs require not only an efficient, high-performance multiply-accumulation (MAC) operation but also an efficient Gaussian random number generator (GRNG) with high-quality statistics. In this article, an NN accelerator chip, leveraging a multi-bit analog compute-in-memory (CiM) static random-access memory (SRAM) macro, with a tightly coupled and highly efficient GRNG scheme, is presented in the Intel 22FFL process. The CiM macro achieves a peak energy efficiency of 32.2 TOP/sW, with 8-bit precision, while ensuring accurate on-chip matrix-vector multiplications (MVMs) with a computation error less than 0.5%. The variable precision GRNG achieves a peak throughput of 7.31 GSamp/s for an energy efficiency of <inline-formula> <tex-math notation="LaTeX">\sim</tex-math> </inline-formula>1 TSamp/J. Overall, our proposed system achieves a peak energy efficiency of 1170 GOP/s/W, a 35-133<inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> improvement over the state-of-the-art BNN accelerators, with 98.14% accuracy for the MNIST dataset.]]></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2023.3283186</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Analog computing ; Artificial neural networks ; Bayesian analysis ; Bayesian neural network (BNN) ; complementary metal–oxide–semiconductor (CMOS) ; compute-in-memory (CiM) ; Energy efficiency ; Field programmable gate arrays ; Gaussian random number generation (GRNG) ; Mathematical analysis ; multiply-accumulate (MAC) operation ; Neural networks ; Random numbers ; Software ; Static random access memory ; System-on-chip ; Systems architecture ; Uncertainty ; weight sampler</subject><ispartof>IEEE journal of solid-state circuits, 2023-10, Vol.58 (10), p.1-13</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c294t-a66968a8b37177498f73cbdba4cb568e0111a93b0b50080377fc2468b16150da3</citedby><cites>FETCH-LOGICAL-c294t-a66968a8b37177498f73cbdba4cb568e0111a93b0b50080377fc2468b16150da3</cites><orcidid>0000-0003-4756-5394 ; 0000-0002-4462-8006 ; 0000-0002-5973-0193 ; 0000-0003-4542-4715</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10153995$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Dorrance, Richard</creatorcontrib><creatorcontrib>Dasalukunte, Deepak</creatorcontrib><creatorcontrib>Wang, Hechen</creatorcontrib><creatorcontrib>Liu, Renzhi</creatorcontrib><creatorcontrib>Carlton, Brent</creatorcontrib><title>An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[Bayesian neural networks (BNNs) have been proposed to address the problems of overfitting and overconfident decision making, common in conventional neural networks (NNs), due to their ability to model and express uncertainty in their predictions. However, BNNs require multiple inference passes to produce the necessary posterior distributions used to generate these highly desirable uncertainty estimates. As such, BNNs require not only an efficient, high-performance multiply-accumulation (MAC) operation but also an efficient Gaussian random number generator (GRNG) with high-quality statistics. In this article, an NN accelerator chip, leveraging a multi-bit analog compute-in-memory (CiM) static random-access memory (SRAM) macro, with a tightly coupled and highly efficient GRNG scheme, is presented in the Intel 22FFL process. The CiM macro achieves a peak energy efficiency of 32.2 TOP/sW, with 8-bit precision, while ensuring accurate on-chip matrix-vector multiplications (MVMs) with a computation error less than 0.5%. The variable precision GRNG achieves a peak throughput of 7.31 GSamp/s for an energy efficiency of <inline-formula> <tex-math notation="LaTeX">\sim</tex-math> </inline-formula>1 TSamp/J. Overall, our proposed system achieves a peak energy efficiency of 1170 GOP/s/W, a 35-133<inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> improvement over the state-of-the-art BNN accelerators, with 98.14% accuracy for the MNIST dataset.]]></description><subject>Analog computing</subject><subject>Artificial neural networks</subject><subject>Bayesian analysis</subject><subject>Bayesian neural network (BNN)</subject><subject>complementary metal–oxide–semiconductor (CMOS)</subject><subject>compute-in-memory (CiM)</subject><subject>Energy efficiency</subject><subject>Field programmable gate arrays</subject><subject>Gaussian random number generation (GRNG)</subject><subject>Mathematical analysis</subject><subject>multiply-accumulate (MAC) operation</subject><subject>Neural networks</subject><subject>Random numbers</subject><subject>Software</subject><subject>Static random access memory</subject><subject>System-on-chip</subject><subject>Systems architecture</subject><subject>Uncertainty</subject><subject>weight sampler</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><recordid>eNpNkM1PAjEQxRujiYj-ASYemnhe7LT70R4R-TKIiUD0tunuzmIVuthdNNz80y2Bg6eXmbz3JvMj5BpYB4Cpu8fZrNfhjIuO4FKAjE9IC6JIBpCIt1PSYgxkoDhj5-Sirj_8GIYSWuS3a2nfolvugn5Zmtygbei93mFttKVT3Dq98tL8VO6TdvMcV-h0Uzn6app32jNPVNuCajo3awzGtkG3Qv2NBR3pQq-1K-iDWZrGlwxfpkO6qI1dUs4Du6YDYwf9-SU5K_WqxqujtsnCb3ujYPI8HPe6kyDnKmwCHccqllpmIoEkCZUsE5FnRabDPItiiQwAtBIZyyLGJBNJUuY8jGUGMUSs0KJNbg-9G1d9bbFu0o9q66w_mXIZK08NEuZdcHDlrqprh2W6cca_sUuBpXvQ6R50ugedHkH7zM0hYxDxnx8ioVQk_gBvWnfG</recordid><startdate>20231001</startdate><enddate>20231001</enddate><creator>Dorrance, Richard</creator><creator>Dasalukunte, Deepak</creator><creator>Wang, Hechen</creator><creator>Liu, Renzhi</creator><creator>Carlton, Brent</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-4756-5394</orcidid><orcidid>https://orcid.org/0000-0002-4462-8006</orcidid><orcidid>https://orcid.org/0000-0002-5973-0193</orcidid><orcidid>https://orcid.org/0000-0003-4542-4715</orcidid></search><sort><creationdate>20231001</creationdate><title>An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET</title><author>Dorrance, Richard ; Dasalukunte, Deepak ; Wang, Hechen ; Liu, Renzhi ; Carlton, Brent</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c294t-a66968a8b37177498f73cbdba4cb568e0111a93b0b50080377fc2468b16150da3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Analog computing</topic><topic>Artificial neural networks</topic><topic>Bayesian analysis</topic><topic>Bayesian neural network (BNN)</topic><topic>complementary metal–oxide–semiconductor (CMOS)</topic><topic>compute-in-memory (CiM)</topic><topic>Energy efficiency</topic><topic>Field programmable gate arrays</topic><topic>Gaussian random number generation (GRNG)</topic><topic>Mathematical analysis</topic><topic>multiply-accumulate (MAC) operation</topic><topic>Neural networks</topic><topic>Random numbers</topic><topic>Software</topic><topic>Static random access memory</topic><topic>System-on-chip</topic><topic>Systems architecture</topic><topic>Uncertainty</topic><topic>weight sampler</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Dorrance, Richard</creatorcontrib><creatorcontrib>Dasalukunte, Deepak</creatorcontrib><creatorcontrib>Wang, Hechen</creatorcontrib><creatorcontrib>Liu, Renzhi</creatorcontrib><creatorcontrib>Carlton, Brent</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Dorrance, Richard</au><au>Dasalukunte, Deepak</au><au>Wang, Hechen</au><au>Liu, Renzhi</au><au>Carlton, Brent</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2023-10-01</date><risdate>2023</risdate><volume>58</volume><issue>10</issue><spage>1</spage><epage>13</epage><pages>1-13</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract><![CDATA[Bayesian neural networks (BNNs) have been proposed to address the problems of overfitting and overconfident decision making, common in conventional neural networks (NNs), due to their ability to model and express uncertainty in their predictions. However, BNNs require multiple inference passes to produce the necessary posterior distributions used to generate these highly desirable uncertainty estimates. As such, BNNs require not only an efficient, high-performance multiply-accumulation (MAC) operation but also an efficient Gaussian random number generator (GRNG) with high-quality statistics. In this article, an NN accelerator chip, leveraging a multi-bit analog compute-in-memory (CiM) static random-access memory (SRAM) macro, with a tightly coupled and highly efficient GRNG scheme, is presented in the Intel 22FFL process. The CiM macro achieves a peak energy efficiency of 32.2 TOP/sW, with 8-bit precision, while ensuring accurate on-chip matrix-vector multiplications (MVMs) with a computation error less than 0.5%. The variable precision GRNG achieves a peak throughput of 7.31 GSamp/s for an energy efficiency of <inline-formula> <tex-math notation="LaTeX">\sim</tex-math> </inline-formula>1 TSamp/J. Overall, our proposed system achieves a peak energy efficiency of 1170 GOP/s/W, a 35-133<inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> improvement over the state-of-the-art BNN accelerators, with 98.14% accuracy for the MNIST dataset.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2023.3283186</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0003-4756-5394</orcidid><orcidid>https://orcid.org/0000-0002-4462-8006</orcidid><orcidid>https://orcid.org/0000-0002-5973-0193</orcidid><orcidid>https://orcid.org/0000-0003-4542-4715</orcidid></addata></record> |
fulltext | fulltext |
identifier | ISSN: 0018-9200 |
ispartof | IEEE journal of solid-state circuits, 2023-10, Vol.58 (10), p.1-13 |
issn | 0018-9200 1558-173X |
language | eng |
recordid | cdi_ieee_primary_10153995 |
source | IEEE Xplore (Online service) |
subjects | Analog computing Artificial neural networks Bayesian analysis Bayesian neural network (BNN) complementary metal–oxide–semiconductor (CMOS) compute-in-memory (CiM) Energy efficiency Field programmable gate arrays Gaussian random number generation (GRNG) Mathematical analysis multiply-accumulate (MAC) operation Neural networks Random numbers Software Static random access memory System-on-chip Systems architecture Uncertainty weight sampler |
title | An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T22%3A37%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=An%20Energy-Efficient%20Bayesian%20Neural%20Network%20Accelerator%20With%20CiM%20and%20a%20Time-Interleaved%20Hadamard%20Digital%20GRNG%20Using%2022-nm%20FinFET&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Dorrance,%20Richard&rft.date=2023-10-01&rft.volume=58&rft.issue=10&rft.spage=1&rft.epage=13&rft.pages=1-13&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2023.3283186&rft_dat=%3Cproquest_ieee_%3E2869328170%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c294t-a66968a8b37177498f73cbdba4cb568e0111a93b0b50080377fc2468b16150da3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=2869328170&rft_id=info:pmid/&rft_ieee_id=10153995&rfr_iscdi=true |