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Curing Process for Passivation Layer of Backside-Illuminated CMOS Image Sensor
We fabricated Al/Al 2 O 3 /SiO 2 /Si and Al/HfO 2 /Si structures to optimize the passivation layer of a backside-illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor (CIS), with the key properties of the newly developed high- k passivation layer analyzed via border traps, in...
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Published in: | IEEE access 2023-06, p.1-1 |
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creator | Park, Jongseo Choi, Kyeong-Keun An, Jehyun Kang, Bohyeon You, Hyeonseo Hong, Giryun Ahn, Sung-Min Baek, Rock-Hyun |
description | We fabricated Al/Al 2 O 3 /SiO 2 /Si and Al/HfO 2 /Si structures to optimize the passivation layer of a backside-illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor (CIS), with the key properties of the newly developed high- k passivation layer analyzed via border traps, interface traps, and fixed charges. In the first experiment using Al 2 O 3 /SiO 2 bilayer-based structures, different thicknesses of SiO 2 were applied from 0 to 15 nm. The improvement in their properties was confirmed by applying forming gas annealing (FGA), a type of post-treatment, to all experimental systems. The first experiment results indicated that both the SiO 2 layer and FGA were effective for chemical passivation. However, a tradeoff occurred in the degree of improvement of the interface trap density (D it ) and fixed-charge density (Q f ) according to the SiO 2 layer thickness. Subsequently, in the second experiment using HfO 2 single-layer-based structures, FGA improved the border trap to a relatively poor extent compared to the first experiment. Nevertheless, FGA improved the electrical characteristics of the HfO 2 films without any side effects and results in optimal D it and |Q f /q| values of 2.59×10 11 eV -1 cm -2 and 1.00×10 12 cm -2 , respectively, demonstrating its potential for the passivation layer in BSI CIS applications. |
doi_str_mv | 10.1109/ACCESS.2023.3286976 |
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In the first experiment using Al 2 O 3 /SiO 2 bilayer-based structures, different thicknesses of SiO 2 were applied from 0 to 15 nm. The improvement in their properties was confirmed by applying forming gas annealing (FGA), a type of post-treatment, to all experimental systems. The first experiment results indicated that both the SiO 2 layer and FGA were effective for chemical passivation. However, a tradeoff occurred in the degree of improvement of the interface trap density (D it ) and fixed-charge density (Q f ) according to the SiO 2 layer thickness. Subsequently, in the second experiment using HfO 2 single-layer-based structures, FGA improved the border trap to a relatively poor extent compared to the first experiment. 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In the first experiment using Al 2 O 3 /SiO 2 bilayer-based structures, different thicknesses of SiO 2 were applied from 0 to 15 nm. The improvement in their properties was confirmed by applying forming gas annealing (FGA), a type of post-treatment, to all experimental systems. The first experiment results indicated that both the SiO 2 layer and FGA were effective for chemical passivation. However, a tradeoff occurred in the degree of improvement of the interface trap density (D it ) and fixed-charge density (Q f ) according to the SiO 2 layer thickness. Subsequently, in the second experiment using HfO 2 single-layer-based structures, FGA improved the border trap to a relatively poor extent compared to the first experiment. Nevertheless, FGA improved the electrical characteristics of the HfO 2 films without any side effects and results in optimal D it and |Q f /q| values of 2.59×10 11 eV -1 cm -2 and 1.00×10 12 cm -2 , respectively, demonstrating its potential for the passivation layer in BSI CIS applications.</abstract><pub>IEEE</pub><doi>10.1109/ACCESS.2023.3286976</doi><orcidid>https://orcid.org/0000-0002-6175-8101</orcidid><orcidid>https://orcid.org/0000-0001-8460-698X</orcidid><orcidid>https://orcid.org/0000-0002-7008-6087</orcidid><orcidid>https://orcid.org/0000-0002-4950-757X</orcidid><oa>free_for_read</oa></addata></record> |
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subjects | Capacitance-voltage characteristics CMOS image sensor forming gas annealing Hafnium oxide HfO<sub xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">2 High-k dielectric materials Passivation plasma-enhanced atomic layer deposition Silicon SiO<sub xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">2 Substrates surface passivation |
title | Curing Process for Passivation Layer of Backside-Illuminated CMOS Image Sensor |
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