Integration of capacitor for sub-100-nm DRAM trench technology

• Main Authors: Lutzen, J., Birner, A., Goldbach, M., Gutsche, M., Hecht, T., Jakschik, S., Orth, A., Sanger, A., Schroder, U., Seidl, H., Sell, B., Schumann, D.
• Format: Conference Proceeding
• Language: English
• Subjects: Applied sciences; Capacitance measurement; Capacitors; Delay; Design. Technologies. Operation analysis. Testing; Dielectric measurements; Dielectric, amorphous and glass solid devices; Electrodes; Electronics; Etching; Exact sciences and technology; High K dielectric materials; High-K gate dielectrics; Integrated circuits; Integrated circuits by function (including memories and processors); Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Technological innovation
• DOI: 10.1109/VLSIT.2002.1015442

One of the key enablers in scaling DRAM trench capacitors to sub-100 nm ground rules is a viable collar integration concept. We report, for the first time, the successful implementation of a buried collar concept, which leaves ample space for the connection from the array device to the inner electrode. The new collar integration scheme is fully compatible with a number of capacitance enhancement techniques including surface enlargement by trench widening, HSG deposition as well as the utilization of high-k node dielectrics such as Al/sub 2/O/sub 3/. These capacitance enhancement techniques are required to maintain a capacitance in excess of 30 fF/cell. In addition, a metal fill of the deep trench is necessary to maintain a low series resistance of the inner electrode, which is also demonstrated for the first time. The successful integration of these key enablers in deep trenches is presented.