An 8b 1.0-to-1.25GS/s Time-Based ADC with Bipolar VTC and Sense Amplifier Latch Interpolated Gated Ring Oscillator TDC

An 8-bit digital intensive time-based ADC implemented in 5nm CMOS is presented in this work. It proposes a bipolar ramp-based voltage-to-time converter (BVTC) to eliminate the reference voltage and to allow a wide input swing of 0.75Vpp,diff. A redundancy scheme for the input polarity decision taken...

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Bibliographic Details
Published in:IEEE solid-state circuits letters 2023-07, p.1-1
Main Authors: Yonar, A. Serdar, Francese, Pier Andrea, Brandli, Matthias, Kossel, Marcel, Prathapan, Mridula, Morf, Thomas, Ruffino, Andrea, Kim, Gain, Jang, Taekwang
Format: Article
Language:English
Subjects:
1/f noise
Calibration
Capacitors
Interpolation
phase interpolation
Redundancy
ring-oscillator
Solid state circuits
Time-based ADC
time-to-digital converter
Voltage
voltage-to-time converter
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Summary:An 8-bit digital intensive time-based ADC implemented in 5nm CMOS is presented in this work. It proposes a bipolar ramp-based voltage-to-time converter (BVTC) to eliminate the reference voltage and to allow a wide input swing of 0.75Vpp,diff. A redundancy scheme for the input polarity decision taken for 1-bit voltage domain folding is introduced against wrong decisions which eliminates comparator calibration in analog domain and allows a more efficient design. Sense amplifier latch (SAL) interpolation technique is presented which reduces the power and area consumption when phase interpolating the time-to-digital converter (TDC) signals. The ADC reaches 1GS/s sampling rate with 0.7V supply and 1.25GS/s with 0.8V supply and achieves 16.6fJ/conv-step and 20.3fJ/conv-step Walden FoM respectively. The total active area is 313μm2.
ISSN:2573-9603
DOI:10.1109/LSSC.2023.3293273