THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE

• Main Authors: Li, Jingyuan, Qiu, Yunhui, Zhu, Guowei, Zhu, Qilong, Yin, Wenbo, Wang, Lingli
• Format: Conference Proceeding
• Language: English
• Subjects: Bayesian Optimization; CGRA framework; Circuits and systems; Delays; Design space exploration; Energy efficiency; Heterogeneous CGRA; Integrated circuit interconnections; Power demand; Reconfigurable architectures; Space exploration
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS46773.2023.10182204

Coarse-grained reconfigurable architecture (CGRA), composed of word-level processing elements (PEs) and interconnects, has emerged as a promising architecture due to its high performance, energy efficiency, and flexibility. Although multiple CGRA frameworks have been proposed, a complete heterogeneous CGRA exploration framework with tunable interconnect flexibility and fast design space exploration (DSE) is still lacking. In this paper, we propose an open-source template-based CGRA exploration framework that integrates the modeling of heterogeneous PEs and interconnects, RTL generation, DFG mapping, automatic simulation and verification, and fast DSE based on a CGRA framework TRAM. Moreover, we present a novel resource-efficient shared reconfigurable delay unit (RDU) for data synchronization, which can save the CGRA area by 7%, compared with the separated RDU. Further, the explored optimal heterogeneous architecture can reduce the area and power by 44.7% and 42.9% respectively, and improve the PE utilization by 20.4%, compared with the 8 × 8 baseline architecture in TRAM.