Loading…

THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE

Coarse-grained reconfigurable architecture (CGRA), composed of word-level processing elements (PEs) and interconnects, has emerged as a promising architecture due to its high performance, energy efficiency, and flexibility. Although multiple CGRA frameworks have been proposed, a complete heterogeneo...

Full description

Saved in:
Bibliographic Details
Main Authors: Li, Jingyuan, Qiu, Yunhui, Zhu, Guowei, Zhu, Qilong, Yin, Wenbo, Wang, Lingli
Format: Conference Proceeding
Language:English
Subjects:
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 5
container_issue
container_start_page 1
container_title
container_volume
creator Li, Jingyuan
Qiu, Yunhui
Zhu, Guowei
Zhu, Qilong
Yin, Wenbo
Wang, Lingli
description Coarse-grained reconfigurable architecture (CGRA), composed of word-level processing elements (PEs) and interconnects, has emerged as a promising architecture due to its high performance, energy efficiency, and flexibility. Although multiple CGRA frameworks have been proposed, a complete heterogeneous CGRA exploration framework with tunable interconnect flexibility and fast design space exploration (DSE) is still lacking. In this paper, we propose an open-source template-based CGRA exploration framework that integrates the modeling of heterogeneous PEs and interconnects, RTL generation, DFG mapping, automatic simulation and verification, and fast DSE based on a CGRA framework TRAM. Moreover, we present a novel resource-efficient shared reconfigurable delay unit (RDU) for data synchronization, which can save the CGRA area by 7%, compared with the separated RDU. Further, the explored optimal heterogeneous architecture can reduce the area and power by 44.7% and 42.9% respectively, and improve the PE utilization by 20.4%, compared with the 8 × 8 baseline architecture in TRAM.
doi_str_mv 10.1109/ISCAS46773.2023.10182204
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_10182204</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10182204</ieee_id><sourcerecordid>10182204</sourcerecordid><originalsourceid>FETCH-LOGICAL-i204t-d801dc9977b21958bcb4229b1d54342b751e2214c6d209997c296b79a7841cb93</originalsourceid><addsrcrecordid>eNo1j81qg0AUhaeFQpO0b9DFvIB27nXGcboTm8RAQmm06zCjt8FWo6ih9O0j_VkdOHx8nMMYB-EDCPO4yZI4k6HWgY8CAx8ERIhCXrE5hKGSaoLwms0QVOSBQnXL5sPwIQQKEeKMvebpPt498Zjn1HS1HclzdqCSpzRS3x7pRO154Ml6H_NdW1JdnY581duGvtr-k2fnrmv78ae0w8ifs-Udu3m39UD3f7lgb6tlnqTe9mW9SeKtV03zRq-MBJSFMVo7BKMiVziJaByUSgYSnVZAiCCLsERhJq5AEzptrI4kFM4EC_bw662I6ND1VWP778P__-ACfE1N1A</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE</title><source>IEEE Xplore All Conference Series</source><creator>Li, Jingyuan ; Qiu, Yunhui ; Zhu, Guowei ; Zhu, Qilong ; Yin, Wenbo ; Wang, Lingli</creator><creatorcontrib>Li, Jingyuan ; Qiu, Yunhui ; Zhu, Guowei ; Zhu, Qilong ; Yin, Wenbo ; Wang, Lingli</creatorcontrib><description>Coarse-grained reconfigurable architecture (CGRA), composed of word-level processing elements (PEs) and interconnects, has emerged as a promising architecture due to its high performance, energy efficiency, and flexibility. Although multiple CGRA frameworks have been proposed, a complete heterogeneous CGRA exploration framework with tunable interconnect flexibility and fast design space exploration (DSE) is still lacking. In this paper, we propose an open-source template-based CGRA exploration framework that integrates the modeling of heterogeneous PEs and interconnects, RTL generation, DFG mapping, automatic simulation and verification, and fast DSE based on a CGRA framework TRAM. Moreover, we present a novel resource-efficient shared reconfigurable delay unit (RDU) for data synchronization, which can save the CGRA area by 7%, compared with the separated RDU. Further, the explored optimal heterogeneous architecture can reduce the area and power by 44.7% and 42.9% respectively, and improve the PE utilization by 20.4%, compared with the 8 × 8 baseline architecture in TRAM.</description><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 1665451092</identifier><identifier>EISBN: 9781665451093</identifier><identifier>DOI: 10.1109/ISCAS46773.2023.10182204</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bayesian Optimization ; CGRA framework ; Circuits and systems ; Delays ; Design space exploration ; Energy efficiency ; Heterogeneous CGRA ; Integrated circuit interconnections ; Power demand ; Reconfigurable architectures ; Space exploration</subject><ispartof>2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10182204$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,23930,23931,25140,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10182204$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Li, Jingyuan</creatorcontrib><creatorcontrib>Qiu, Yunhui</creatorcontrib><creatorcontrib>Zhu, Guowei</creatorcontrib><creatorcontrib>Zhu, Qilong</creatorcontrib><creatorcontrib>Yin, Wenbo</creatorcontrib><creatorcontrib>Wang, Lingli</creatorcontrib><title>THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE</title><title>2023 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>Coarse-grained reconfigurable architecture (CGRA), composed of word-level processing elements (PEs) and interconnects, has emerged as a promising architecture due to its high performance, energy efficiency, and flexibility. Although multiple CGRA frameworks have been proposed, a complete heterogeneous CGRA exploration framework with tunable interconnect flexibility and fast design space exploration (DSE) is still lacking. In this paper, we propose an open-source template-based CGRA exploration framework that integrates the modeling of heterogeneous PEs and interconnects, RTL generation, DFG mapping, automatic simulation and verification, and fast DSE based on a CGRA framework TRAM. Moreover, we present a novel resource-efficient shared reconfigurable delay unit (RDU) for data synchronization, which can save the CGRA area by 7%, compared with the separated RDU. Further, the explored optimal heterogeneous architecture can reduce the area and power by 44.7% and 42.9% respectively, and improve the PE utilization by 20.4%, compared with the 8 × 8 baseline architecture in TRAM.</description><subject>Bayesian Optimization</subject><subject>CGRA framework</subject><subject>Circuits and systems</subject><subject>Delays</subject><subject>Design space exploration</subject><subject>Energy efficiency</subject><subject>Heterogeneous CGRA</subject><subject>Integrated circuit interconnections</subject><subject>Power demand</subject><subject>Reconfigurable architectures</subject><subject>Space exploration</subject><issn>2158-1525</issn><isbn>1665451092</isbn><isbn>9781665451093</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2023</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1j81qg0AUhaeFQpO0b9DFvIB27nXGcboTm8RAQmm06zCjt8FWo6ih9O0j_VkdOHx8nMMYB-EDCPO4yZI4k6HWgY8CAx8ERIhCXrE5hKGSaoLwms0QVOSBQnXL5sPwIQQKEeKMvebpPt498Zjn1HS1HclzdqCSpzRS3x7pRO154Ml6H_NdW1JdnY581duGvtr-k2fnrmv78ae0w8ifs-Udu3m39UD3f7lgb6tlnqTe9mW9SeKtV03zRq-MBJSFMVo7BKMiVziJaByUSgYSnVZAiCCLsERhJq5AEzptrI4kFM4EC_bw662I6ND1VWP778P__-ACfE1N1A</recordid><startdate>20230521</startdate><enddate>20230521</enddate><creator>Li, Jingyuan</creator><creator>Qiu, Yunhui</creator><creator>Zhu, Guowei</creator><creator>Zhu, Qilong</creator><creator>Yin, Wenbo</creator><creator>Wang, Lingli</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20230521</creationdate><title>THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE</title><author>Li, Jingyuan ; Qiu, Yunhui ; Zhu, Guowei ; Zhu, Qilong ; Yin, Wenbo ; Wang, Lingli</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i204t-d801dc9977b21958bcb4229b1d54342b751e2214c6d209997c296b79a7841cb93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Bayesian Optimization</topic><topic>CGRA framework</topic><topic>Circuits and systems</topic><topic>Delays</topic><topic>Design space exploration</topic><topic>Energy efficiency</topic><topic>Heterogeneous CGRA</topic><topic>Integrated circuit interconnections</topic><topic>Power demand</topic><topic>Reconfigurable architectures</topic><topic>Space exploration</topic><toplevel>online_resources</toplevel><creatorcontrib>Li, Jingyuan</creatorcontrib><creatorcontrib>Qiu, Yunhui</creatorcontrib><creatorcontrib>Zhu, Guowei</creatorcontrib><creatorcontrib>Zhu, Qilong</creatorcontrib><creatorcontrib>Yin, Wenbo</creatorcontrib><creatorcontrib>Wang, Lingli</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library Online</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Li, Jingyuan</au><au>Qiu, Yunhui</au><au>Zhu, Guowei</au><au>Zhu, Qilong</au><au>Yin, Wenbo</au><au>Wang, Lingli</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE</atitle><btitle>2023 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2023-05-21</date><risdate>2023</risdate><spage>1</spage><epage>5</epage><pages>1-5</pages><eissn>2158-1525</eissn><eisbn>1665451092</eisbn><eisbn>9781665451093</eisbn><abstract>Coarse-grained reconfigurable architecture (CGRA), composed of word-level processing elements (PEs) and interconnects, has emerged as a promising architecture due to its high performance, energy efficiency, and flexibility. Although multiple CGRA frameworks have been proposed, a complete heterogeneous CGRA exploration framework with tunable interconnect flexibility and fast design space exploration (DSE) is still lacking. In this paper, we propose an open-source template-based CGRA exploration framework that integrates the modeling of heterogeneous PEs and interconnects, RTL generation, DFG mapping, automatic simulation and verification, and fast DSE based on a CGRA framework TRAM. Moreover, we present a novel resource-efficient shared reconfigurable delay unit (RDU) for data synchronization, which can save the CGRA area by 7%, compared with the separated RDU. Further, the explored optimal heterogeneous architecture can reduce the area and power by 44.7% and 42.9% respectively, and improve the PE utilization by 20.4%, compared with the 8 × 8 baseline architecture in TRAM.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS46773.2023.10182204</doi><tpages>5</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier EISSN: 2158-1525
ispartof 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5
issn 2158-1525
language eng
recordid cdi_ieee_primary_10182204
source IEEE Xplore All Conference Series
subjects Bayesian Optimization
CGRA framework
Circuits and systems
Delays
Design space exploration
Energy efficiency
Heterogeneous CGRA
Integrated circuit interconnections
Power demand
Reconfigurable architectures
Space exploration
title THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-23T10%3A35%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=THRAM:%20A%20Template-based%20Heterogeneous%20CGRA%20Modeling%20Framework%20Supporting%20Fast%20DSE&rft.btitle=2023%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Li,%20Jingyuan&rft.date=2023-05-21&rft.spage=1&rft.epage=5&rft.pages=1-5&rft.eissn=2158-1525&rft_id=info:doi/10.1109/ISCAS46773.2023.10182204&rft.eisbn=1665451092&rft.eisbn_list=9781665451093&rft_dat=%3Cieee_CHZPO%3E10182204%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i204t-d801dc9977b21958bcb4229b1d54342b751e2214c6d209997c296b79a7841cb93%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=10182204&rfr_iscdi=true