IMPACT: an architectural framework for multiple-instruction-issue processors

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Bibliographic Details
Main Authors: Chang, P.P., Mahike, S.A., Chen, W.Y., Warier, N.J., Hwu, W.W.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Concurrent computing
Delay
Hardware
Optimizing compilers
Permission
Pipeline processing
Processor scheduling
Radio access networks
Registers
Online Access:Request full text
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ISSN:0163-5964
DOI:10.1145/115952.115979