A 6 K GaAs gate array with fully functional LSI personalization

A 12*12 multiplier consisting of 19000 devices was successfully implemented on a 6000-gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160 de...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1988-04, Vol.23 (2), p.581-590
Main Authors: Peczalski, A., Lee, G., Betten, W.R., Somal, H., Plagens, M., Biard, J.R., Burrows, I., Gilbert, B.K., Thompson, R.L., Naused, B.A., Karwoski, S.M., Samson, M.L., Zahn, S.K.
Format: Article
Language:English
Subjects:
Circuit faults
Circuit noise
Circuit synthesis
Contamination
Fabrication
Gallium arsenide
Large scale integration
Pollution measurement
Temperature distribution
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Summary:A 12*12 multiplier consisting of 19000 devices was successfully implemented on a 6000-gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160 degrees C range. The backgating and dynamic (switching) noise are also discussed as the key noise-margin limiting factors. A specialized on-chip circuitry which enables on-chip measurement and fault localization in complex GaAs ICs is proposed and implemented. The high yield of the multiplier (10%) seems to be limited only by particle contamination, which indicates that the noise margin is satisfactory for the GaAs nonselfaligned depletion-mode fabrication process.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.1025