Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments

• Main Authors: Makimoto, Renya, Imagawa, Takashi, Ochi, Hiroyuki
• Format: Conference Proceeding
• Language: English
• Subjects: Adders; Costs; Image recognition; Linear approximation; logarithmic number system; Mitchell's approximate logarithmic multiplier; piece-wise linear approximation; System-on-chip
• ISSN: 2164-1706
• DOI: 10.1109/SOCC58585.2023.10256796

This paper proposes an asymmetric compensation approach for log and antilog transformations to realize approximate multipliers with an improved area-accuracy trade-off. Since multipliers consume a larger area and power than adders/subtractors, research has been conducted on approximate multipliers that reduce the area and power by allowing errors that are acceptable for applications. Especially in recent years, the demand for multiplication that does not require the exact product has been increasing in some application domains, including image processing and image recognition. The approximate logarithmic multiplier proposed by Mitchell introduced a linear approximation to each interval (2 k , 2 k+1 ) of log 2 . Because it can be implemented with simple shifters and adders, the area and power are reduced compared to the exact multiplier, at the cost of 11.1% maximum error. This paper introduces a two-segment piecewise-linear compensation to Mitchell's logarithmic multiplier to improve the accuracy. We also conducted design-space exploration, including asymmetric compensations for the log and antilog transformations. We propose an HC-7 (half compensation with 7-bit truncation) multiplier that applies compensation using two segments of slopes 9/8 and 7/8 and 7-bit truncation during log transformation and does not apply compensation during antilog. Compared to DRUM, the 16-bit HC-7 multiplier achieved ×0.85 reduced worst-case relative error (WCRE) with a 15% reduction of circuit area.