A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS

This work presents a 2x Time-Interleaved (TI) Delta Sigma Modulator (DSM) Analog-to-Digital Converter (ADC) leveraging a 6b Noise-Coupled (NC) Noise-Shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck on a 2xTI NC...

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Bibliographic Details
Main Authors: Santana, Lucas Moura, Martens, Ewout, Lagos, Jorge, Wambacq, Piet, Craninckx, Jan
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Capacitors
Degradation
delta-sigma ADC
Linearity
Noise reduction
Noise shaping
noise-shaping SAR
ringamp
Sigma-delta modulation
time-interleaved ADC
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Summary:This work presents a 2x Time-Interleaved (TI) Delta Sigma Modulator (DSM) Analog-to-Digital Converter (ADC) leveraging a 6b Noise-Coupled (NC) Noise-Shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck on a 2xTI NC NS SAR, having minimal impact on the achievable clock speed. The loop filter is implemented using power-efficient no-hold phase ringamps with an input capacitor reset pre-sampling to reduce kickback noise in the input network. The full ADC clocks at a sampling rate of 1. 4GS/s which is the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date and achieves 67dB/72dBSNDR/SNR over a 70MHz bandwidth while consuming 32mW.
ISSN:2643-1319
DOI:10.1109/ESSCIRC59616.2023.10268759