FeFET Reliability Modeling for In-Memory Computing: Challenges, Perspective, and Emerging Trends

• Published in: IEEE transactions on electron devices 2024-01, Vol.71 (1), p.287-293
• Main Authors: Thomann, Simon, Amrouch, Hussam
• Format: Article
• Language: English
• Subjects: Algorithms; Binary neural network (BNN); Computation; Error analysis; FeFETs; ferroelectric (FE); ferroelectric FET (FeFET); Ferroelectricity; Hardware; hyperdimensional computing (HDC); Iron; Machine learning; Modelling; MOSFET; multidomain; Neural networks; New technology; Pattern recognition; Reliability; Reliability analysis; Resilience; Robustness; Silicon-on-insulator; technology CAD (TCAD); Temperature; variation
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2023.3313112

Ferroelectric FET (FeFET) is a singularly attractive emerging technology with a rich feature set. Boasting high versatility, it has already been implemented in a host of applications, like dense memory arrays and in-memory computing (IMC). Nevertheless, being an emerging technology, FeFETs are faced with reliability concerns that warrant analysis and mitigation. As a first step, modeling the FeFET variability can help to ascertain its present applicability. For instance, binary neural networks (BNNs) are more error resilient than classical deep-neural networks implementations and thus, can utilize this emerging yet unreliable hardware. However, conventional machine learning (ML) still relies on large datasets for training that need to be processed many times by the algorithm, exposing the memory wall of the von Neumann architecture. This necessitates the pursuit of new computing paradigms, like hyperdimensional computing (HDC). HDC is an emerging brain-inspired ML algorithm that can learn from very little data, using pattern recognition and randomness as its core working principles. Thus, it is inherently robust against noise and errors in the employed computing hardware. Hence, the robust HDC and the efficient yet unreliable FeFET are fiercely symbiotic. In this work, we will cover the challenges of the emerging FeFET technology and how to model them on a device level. We will then make use of these models and inject them into applications to study their error resiliency. For this, we will use the aforementioned applications of BNNs and HDC, and showcase their response to the unreliable hardware.