Multicore Spiking Neuromorphic Chip in 180-nm with ReRAM Synapses and Digital Neurons

Neuromorphic computing based on spike neural networks (SNNs) exhibits great potential in reducing energy consumption in hardware systems. Resistive random-access memory (ReRAM) is regarded as a promising candidate to construct neuromorphic hardware, attributing to their high-density, nonvolatile, an...

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Published in:IEEE journal on emerging and selected topics in circuits and systems 2023-12, Vol.13 (4), p.1-1
Main Authors: Jiang, Hao, Lu, Jikai, Zhang, Chenggao, Tang, Shuangzhu, An, Junjie, Cheng, Lingli, Lu, Jian, Wei, Jinsong, Zhou, Keji, Zhang, Xumeng, Shi, Tuo, Liu, Qi
Format: Article
Language:English
Subjects:
Biological system modeling
Brain modeling
Computational modeling
Compute-in-memory
Computer architecture
Density
Digital neuron
Energy consumption
Hardware
Multicore
Multicore processing
Network-on-chip
Neural networks
Neuromorphic computing
Neurons
Random access memory
ReRAM
SNN
Synapses
System on chip
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Summary:Neuromorphic computing based on spike neural networks (SNNs) exhibits great potential in reducing energy consumption in hardware systems. Resistive random-access memory (ReRAM) is regarded as a promising candidate to construct neuromorphic hardware, attributing to their high-density, nonvolatile, and compute-in-memory capability. However, the ReRAM-based neuromorphic chips are still in their infancy, cannot support multicore or with limited neuron configurability. To alleviate these problems, we propose a hybrid multicore SNN chip based on 60 K-ReRAM synapses and 480-digital neurons in the 180 nm node, achieving a synaptic density of 20K bit/mm 2 per core. To improve the efficiency of inter-core communication, we adopt a network-on-chip architecture with a bit character encoding strategy. In addition, an adaptive multiplier-less digital neuron is designed to support both Izhikevich and leaky integrate-and-fire models through register bit control, meeting different application scenarios. Finally, we evaluate the performance of our chip on the MNIST dataset recognition tasks, achieving 97.65% accuracy. Also, a minimum energy per synaptic operation (SOP) of 6.6 pJ in the 180 nm node is obtained, outperforming the TrueNorth's 26 pJ in 28 nm. These results show that our design has a great potential for large-scale SNN implementations and may pave the way for designing high-efficient neuromorphic hardware with ReRAM technology.
ISSN:2156-3357
2156-3365
DOI:10.1109/JETCAS.2023.3325158