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A Power Supply Rejection Based Approach for Robust Defect Detection in Operational Amplifiers
This manuscript presents a comprehensive all-digital design for testability (DfT) approach which achieves high coverage in detecting defects in operational amplifiers (op amps) along with their reference and bias circuits. The proposed method has the capability of been applied both at production tes...
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creator | Sekyere, Michael Saikiran, Marampally Chen, Degang |
description | This manuscript presents a comprehensive all-digital design for testability (DfT) approach which achieves high coverage in detecting defects in operational amplifiers (op amps) along with their reference and bias circuits. The proposed method has the capability of been applied both at production test and for on-line health monitoring post-deployment to detect zero-time and latent defects. The built-in self-test (BIST) circuitry is simple to design, occupies negligible area and exerts minimal to no influence on the op amp's regular performance. The proposed method is based primarily on DC parametric sweep which significantly shortens the test time and consequently leads to a substantial reduction in production test costs. Additionally, due to the digital nature of the method, it can also easily be implemented with existing digital testing infrastructure like IJTAG on a system on chip (SOC). Furthermore, in this work we introduce the duo digital window comparator, a novel detector for testing defects in the Widlar reference and the bias circuitry. We validate our method using extensive transistor-level simulation of a two-stage miller compensated folded cascode amplifier along with widlar reference and current bias circuit. Simulation results show that proposed method achieves a high defect coverage of 99% in main amplifier and 100% in widlar reference and bias circuitry. All the designs in this work are implemented in TSMC 180nm technology. |
doi_str_mv | 10.1109/EWDTS59469.2023.10297071 |
format | conference_proceeding |
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The proposed method has the capability of been applied both at production test and for on-line health monitoring post-deployment to detect zero-time and latent defects. The built-in self-test (BIST) circuitry is simple to design, occupies negligible area and exerts minimal to no influence on the op amp's regular performance. The proposed method is based primarily on DC parametric sweep which significantly shortens the test time and consequently leads to a substantial reduction in production test costs. Additionally, due to the digital nature of the method, it can also easily be implemented with existing digital testing infrastructure like IJTAG on a system on chip (SOC). Furthermore, in this work we introduce the duo digital window comparator, a novel detector for testing defects in the Widlar reference and the bias circuitry. We validate our method using extensive transistor-level simulation of a two-stage miller compensated folded cascode amplifier along with widlar reference and current bias circuit. Simulation results show that proposed method achieves a high defect coverage of 99% in main amplifier and 100% in widlar reference and bias circuitry. All the designs in this work are implemented in TSMC 180nm technology.</description><identifier>EISSN: 2472-761X</identifier><identifier>EISBN: 9798350314847</identifier><identifier>DOI: 10.1109/EWDTS59469.2023.10297071</identifier><language>eng</language><publisher>IEEE</publisher><subject>Built-in self-test ; defect coverage ; Detectors ; DPPM ; on-line health monitoring ; operational amplifier ; Operational amplifiers ; Power supplies ; Production ; Real-time systems ; Simulation</subject><ispartof>2023 IEEE East-West Design & Test Symposium (EWDTS), 2023, p.1-6</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10297071$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,27924,54554,54931</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10297071$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sekyere, Michael</creatorcontrib><creatorcontrib>Saikiran, Marampally</creatorcontrib><creatorcontrib>Chen, Degang</creatorcontrib><title>A Power Supply Rejection Based Approach for Robust Defect Detection in Operational Amplifiers</title><title>2023 IEEE East-West Design & Test Symposium (EWDTS)</title><addtitle>EWDTS</addtitle><description>This manuscript presents a comprehensive all-digital design for testability (DfT) approach which achieves high coverage in detecting defects in operational amplifiers (op amps) along with their reference and bias circuits. The proposed method has the capability of been applied both at production test and for on-line health monitoring post-deployment to detect zero-time and latent defects. The built-in self-test (BIST) circuitry is simple to design, occupies negligible area and exerts minimal to no influence on the op amp's regular performance. The proposed method is based primarily on DC parametric sweep which significantly shortens the test time and consequently leads to a substantial reduction in production test costs. Additionally, due to the digital nature of the method, it can also easily be implemented with existing digital testing infrastructure like IJTAG on a system on chip (SOC). Furthermore, in this work we introduce the duo digital window comparator, a novel detector for testing defects in the Widlar reference and the bias circuitry. We validate our method using extensive transistor-level simulation of a two-stage miller compensated folded cascode amplifier along with widlar reference and current bias circuit. Simulation results show that proposed method achieves a high defect coverage of 99% in main amplifier and 100% in widlar reference and bias circuitry. All the designs in this work are implemented in TSMC 180nm technology.</description><subject>Built-in self-test</subject><subject>defect coverage</subject><subject>Detectors</subject><subject>DPPM</subject><subject>on-line health monitoring</subject><subject>operational amplifier</subject><subject>Operational amplifiers</subject><subject>Power supplies</subject><subject>Production</subject><subject>Real-time systems</subject><subject>Simulation</subject><issn>2472-761X</issn><isbn>9798350314847</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2023</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1kN9KwzAcRqMgOGbfwIu8QGf-NElzWbfphMFkm-iNjKT5BTO6NaQdsre34rw6HDh8Fx9CmJIJpUQ_zN9n243QhdQTRhifUMK0IopeoUwrXXJBOC3KQl2jESsUy5WkH7co67o9IYRKKjSjI_RZ4df2GxLenGJszngNe6j70B7xo-nA4SrG1Jr6C_s24XVrT12PZ-CHZkB_ScMRryIk8yumwdUhNsEHSN0duvGm6SC7cIzenubb6SJfrp5fptUyD5TqPndWW2mlMFpbRb0AJwpXGwfGcmF9yVzNTCm4qmshpQE3iOGeecZ1UZqSj9H9324AgF1M4WDSeff_CP8BWChXlg</recordid><startdate>20230922</startdate><enddate>20230922</enddate><creator>Sekyere, Michael</creator><creator>Saikiran, Marampally</creator><creator>Chen, Degang</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20230922</creationdate><title>A Power Supply Rejection Based Approach for Robust Defect Detection in Operational Amplifiers</title><author>Sekyere, Michael ; Saikiran, Marampally ; Chen, Degang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i119t-db9b6b65a99b71f5ed54dcadeab35bf82dc2a8537cc566aeda85a3f2f23948a83</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Built-in self-test</topic><topic>defect coverage</topic><topic>Detectors</topic><topic>DPPM</topic><topic>on-line health monitoring</topic><topic>operational amplifier</topic><topic>Operational amplifiers</topic><topic>Power supplies</topic><topic>Production</topic><topic>Real-time systems</topic><topic>Simulation</topic><toplevel>online_resources</toplevel><creatorcontrib>Sekyere, Michael</creatorcontrib><creatorcontrib>Saikiran, Marampally</creatorcontrib><creatorcontrib>Chen, Degang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sekyere, Michael</au><au>Saikiran, Marampally</au><au>Chen, Degang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Power Supply Rejection Based Approach for Robust Defect Detection in Operational Amplifiers</atitle><btitle>2023 IEEE East-West Design & Test Symposium (EWDTS)</btitle><stitle>EWDTS</stitle><date>2023-09-22</date><risdate>2023</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><eissn>2472-761X</eissn><eisbn>9798350314847</eisbn><abstract>This manuscript presents a comprehensive all-digital design for testability (DfT) approach which achieves high coverage in detecting defects in operational amplifiers (op amps) along with their reference and bias circuits. The proposed method has the capability of been applied both at production test and for on-line health monitoring post-deployment to detect zero-time and latent defects. The built-in self-test (BIST) circuitry is simple to design, occupies negligible area and exerts minimal to no influence on the op amp's regular performance. The proposed method is based primarily on DC parametric sweep which significantly shortens the test time and consequently leads to a substantial reduction in production test costs. Additionally, due to the digital nature of the method, it can also easily be implemented with existing digital testing infrastructure like IJTAG on a system on chip (SOC). Furthermore, in this work we introduce the duo digital window comparator, a novel detector for testing defects in the Widlar reference and the bias circuitry. We validate our method using extensive transistor-level simulation of a two-stage miller compensated folded cascode amplifier along with widlar reference and current bias circuit. Simulation results show that proposed method achieves a high defect coverage of 99% in main amplifier and 100% in widlar reference and bias circuitry. All the designs in this work are implemented in TSMC 180nm technology.</abstract><pub>IEEE</pub><doi>10.1109/EWDTS59469.2023.10297071</doi><tpages>6</tpages></addata></record> |
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identifier | EISSN: 2472-761X |
ispartof | 2023 IEEE East-West Design & Test Symposium (EWDTS), 2023, p.1-6 |
issn | 2472-761X |
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source | IEEE Xplore All Conference Series |
subjects | Built-in self-test defect coverage Detectors DPPM on-line health monitoring operational amplifier Operational amplifiers Power supplies Production Real-time systems Simulation |
title | A Power Supply Rejection Based Approach for Robust Defect Detection in Operational Amplifiers |
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