Validated 90nm CMOS technology platform with low-k copper interconnects for advanced system-on-chip (SoC)

This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16/spl Aring/ EOT-70nm transistors (standard process) or 21/spl Aring/-90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD...

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Main Authors: Devoivre, T., Lunenborg, M., Julien, C., Carrere, J.-P., Ferreira, P., Toren, W.J., VandeGoor, A., Gayet, P., Berger, T., Hinsinger, O., Vannier, P., Trouiller, Y., Rody, Y., Goirand, P.-J., Palla, R., Thomas, I., Guyader, F., Roy, D., Borot, B., Planes, N., Naudet, S., Pico, F., Duca, D., Lalanne, F., Heslinga, D., Haond, M.
Format: Conference Proceeding
Language:English
Subjects:
CMOS process
CMOS technology
Copper
Energy management
Integrated circuit interconnections
Power supplies
Random access memory
System performance
System-on-a-chip
Technology management
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Summary:This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16/spl Aring/ EOT-70nm transistors (standard process) or 21/spl Aring/-90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1 Mbit SRAM instances, based on a highly manufacturable 6T 1.36/spl mu/m/sup 2/ memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.
ISSN:1087-4852
2576-9154
DOI:10.1109/MTDT.2002.1029778