A low-power CMOS mixer for low-IF receivers

A low-power UHF-to-low-IF downconversion mixer was implemented in a 0.5-/spl mu/m CMOS process. This mixer is designed as the second-block of an integrated low-IF receiver under development for deep space applications. The mixer dissipates 5.4 mW from a 2.5-V supply. LO power requirement is -10 dBm....

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Bibliographic Details
Main Authors: Zencir, E., Dogan, N.S., Arvas, E.
Format: Conference Proceeding
Language:English
Subjects:
CMOS process
Local oscillators
Mixers
Noise figure
Power dissipation
Radio frequency
Resistors
Topology
Transceivers
Voltage
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Summary:A low-power UHF-to-low-IF downconversion mixer was implemented in a 0.5-/spl mu/m CMOS process. This mixer is designed as the second-block of an integrated low-IF receiver under development for deep space applications. The mixer dissipates 5.4 mW from a 2.5-V supply. LO power requirement is -10 dBm. Voltage conversion gain is 20.8 dB. Single side-band noise figure is 9.2 dB at 2 MHz IF. Input 1-dB compression point is -21 dBm while the IIP3 point is at -13.4 dBm. The entire mixer occupies a die area of 0.3 mm /spl times/ 0.26 mm. Low-power dissipation makes this mixer attractive for low-power highly integrated receiver applications.
DOI:10.1109/RAWCON.2002.1030141