Signal/Power Integrity Co-Simulation of Die-to-Die Interface Customized for Augmented Reality

There is a rising demand for customized accelerate-and-compute hardware in emerging augmented reality (AR) and virtual reality (VR) wearables to enable the next generation computing platforms. Customized die-to-die interconnects, critical in heterogeneous system integration, provide significant flex...

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Bibliographic Details
Main Authors: Hashemi, Ashkan, Yamaguchi, Koichi, Bozorgzadeh, Bardia, Jiang, Ling, Manjunath, Harsha, Ahmadi, Mahmoud Reza, Beyene, Wendemgegnehu
Format: Conference Proceeding
Language:English
Subjects:
augmented reality
chiplet
die-to-die interconnect
Object recognition
Sensitivity analysis
SI/PI co-simulation
Silicon
System integration
System performance
Thermal factors
Wearable computers
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Summary:There is a rising demand for customized accelerate-and-compute hardware in emerging augmented reality (AR) and virtual reality (VR) wearables to enable the next generation computing platforms. Customized die-to-die interconnects, critical in heterogeneous system integration, provide significant flexibility in architecture definition and efficient data transfer with potential power advantage. Although custom silicon (and heterogeneous design) is crucial to meet key performance indicators such as power/performance, thermal envelope, and miniscule form factor in AR devices, it poses challenges for robust system design particularly in the context of high-speed signal integrity (SI) and power integrity (PI) considerations. To address these unique challenges, accurate signal and power integrity co-simulation is critical to ensure intact system performance. This paper highlights SI/PI co-simulations required to address the unique challenges applicable to custom die-to-die interface for AR/VR devices.
ISSN:2165-4115
DOI:10.1109/EPEPS58208.2023.10314868