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A Framework-Compatible Hierarchical Railway Power Regulation Strategy With the Integration of Energy Storage-Embedded Railway Power Flow Controller

Intelligent power regulation is a prominent feature of smart railway power systems (RPSs). To achieve this target, the energy storage-embedded railway power flow controller (ES-RPFC) can be adopted, as it provides an effective solution for demand management (DM) and power quality (PQ) improvement. I...

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Bibliographic Details
Published in:IEEE transactions on transportation electrification 2024-09, Vol.10 (3), p.7297-7309
Main Authors: Lin, Jinjie, Hu, Sijia, Li, Yong, Zhang, Jing, Zhang, Jie, Yu, Jiahua
Format: Article
Language:English
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Summary:Intelligent power regulation is a prominent feature of smart railway power systems (RPSs). To achieve this target, the energy storage-embedded railway power flow controller (ES-RPFC) can be adopted, as it provides an effective solution for demand management (DM) and power quality (PQ) improvement. In practice, those two functions of ES-RPFC are often implemented in two native less-compatible frameworks, and the converter rating, which significantly influences the whole system's investment, is seldom considered. These deficiencies diminish the global performance of the whole system. To address them, a novel power regulation strategy is proposed. In this strategy, 1) a unified analytic mathematical framework is first proposed for ES-RPFC's compatibility improvement on both DM and PQ control, which is also beneficial for calculation efficiency improvement; and 2) a hierarchical control strategy is developed upon the framework in 1). This strategy enables compatible implementation of DM and PQ control with minimized back-to-back converter (BTBC) rating while making the RPS exhibit satisfactory grid-connection performance. A comprehensive measured data-based performance evaluation for the proposal is carried out, and the results show that compared with the traditional method, the BTBC rating is reduced by almost 43% in the studied case. Moreover, the proposal's real-time implementation feasibility is verified by hardware-in-the-loop (HIL) tests.
ISSN:2332-7782
2577-4212
2332-7782
DOI:10.1109/TTE.2023.3337268