An accelerated digital CNN-UM (CASTLE) architecture by using the pipe-line technique

Different CNN-UM architecture implementations, analog and emulated digital, were developed. The emulated digital architecture (CASTLE) is accurate but slower than the analog CNN-UMs. It is generally disadvantageous especially if transient computing is critical. The operation speed of the emulated di...

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Bibliographic Details
Main Authors: Hidvegi, T., Keresztes, P., Solgay, P.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Arithmetic
Automation
Cellular neural networks
Computational modeling
Computer architecture
Field programmable gate arrays
Image processing
Registers
System testing
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Summary:Different CNN-UM architecture implementations, analog and emulated digital, were developed. The emulated digital architecture (CASTLE) is accurate but slower than the analog CNN-UMs. It is generally disadvantageous especially if transient computing is critical. The operation speed of the emulated digital implementations, namely CASTLE, can be increased significantly using the pipeline technique. This solution is analyzed with respect to area, time, etc. These arithmetic cores were tested and simulated using a VIRTEX FPGA development system.
DOI:10.1109/CNNA.2002.1035070