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An accelerated digital CNN-UM (CASTLE) architecture by using the pipe-line technique
Different CNN-UM architecture implementations, analog and emulated digital, were developed. The emulated digital architecture (CASTLE) is accurate but slower than the analog CNN-UMs. It is generally disadvantageous especially if transient computing is critical. The operation speed of the emulated di...
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| creator | Hidvegi, T. Keresztes, P. Solgay, P. |
| description | Different CNN-UM architecture implementations, analog and emulated digital, were developed. The emulated digital architecture (CASTLE) is accurate but slower than the analog CNN-UMs. It is generally disadvantageous especially if transient computing is critical. The operation speed of the emulated digital implementations, namely CASTLE, can be increased significantly using the pipeline technique. This solution is analyzed with respect to area, time, etc. These arithmetic cores were tested and simulated using a VIRTEX FPGA development system. |
| doi_str_mv | 10.1109/CNNA.2002.1035070 |
| format | conference_proceeding |
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The emulated digital architecture (CASTLE) is accurate but slower than the analog CNN-UMs. It is generally disadvantageous especially if transient computing is critical. The operation speed of the emulated digital implementations, namely CASTLE, can be increased significantly using the pipeline technique. This solution is analyzed with respect to area, time, etc. These arithmetic cores were tested and simulated using a VIRTEX FPGA development system.</description><subject>Acceleration</subject><subject>Arithmetic</subject><subject>Automation</subject><subject>Cellular neural networks</subject><subject>Computational modeling</subject><subject>Computer architecture</subject><subject>Field programmable gate arrays</subject><subject>Image processing</subject><subject>Registers</subject><subject>System testing</subject><isbn>9789812381217</isbn><isbn>981238121X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2002</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj09rhDAUxAOl0LL1A5RecmwPbvPyTEyOIts_YLeHuucl6nNNsWI1HvbbV-gODHMY5gfD2D2ILYCwz_l-n22lEHILApVIxRWLbGqsAYmrIb1h0Tx_i1XSrov0lpXZwF1dU0-TC9Twxp98cD1fUfHhgz_m2VdZ7J64m-rOB6rDMhGvznyZ_XDioSM--pHi3g_E17ob_O9Cd-y6df1M0SU37PCyK_O3uPh8fc-zIvaQqhArqKRzoCo0BqUyrQGjmwSNRdRWtkpqbVIEBEu6brHSAC0JlZhGUWUS3LCHf64nouM4-R83nY-X7_gHlfZMNQ</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>Hidvegi, T.</creator><creator>Keresztes, P.</creator><creator>Solgay, P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2002</creationdate><title>An accelerated digital CNN-UM (CASTLE) architecture by using the pipe-line technique</title><author>Hidvegi, T. ; Keresztes, P. ; Solgay, P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-51b2aa15b3883258f8186d438933692f52668731319e6cf3b611fe0548d5eb843</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Acceleration</topic><topic>Arithmetic</topic><topic>Automation</topic><topic>Cellular neural networks</topic><topic>Computational modeling</topic><topic>Computer architecture</topic><topic>Field programmable gate arrays</topic><topic>Image processing</topic><topic>Registers</topic><topic>System testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Hidvegi, T.</creatorcontrib><creatorcontrib>Keresztes, P.</creatorcontrib><creatorcontrib>Solgay, P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hidvegi, T.</au><au>Keresztes, P.</au><au>Solgay, P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An accelerated digital CNN-UM (CASTLE) architecture by using the pipe-line technique</atitle><btitle>Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications</btitle><stitle>CNNA</stitle><date>2002</date><risdate>2002</risdate><spage>355</spage><epage>362</epage><pages>355-362</pages><isbn>9789812381217</isbn><isbn>981238121X</isbn><abstract>Different CNN-UM architecture implementations, analog and emulated digital, were developed. The emulated digital architecture (CASTLE) is accurate but slower than the analog CNN-UMs. It is generally disadvantageous especially if transient computing is critical. The operation speed of the emulated digital implementations, namely CASTLE, can be increased significantly using the pipeline technique. This solution is analyzed with respect to area, time, etc. These arithmetic cores were tested and simulated using a VIRTEX FPGA development system.</abstract><pub>IEEE</pub><doi>10.1109/CNNA.2002.1035070</doi><tpages>8</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Acceleration Arithmetic Automation Cellular neural networks Computational modeling Computer architecture Field programmable gate arrays Image processing Registers System testing |
| title | An accelerated digital CNN-UM (CASTLE) architecture by using the pipe-line technique |
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