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Spatial Attention Enhanced Wafer Defect Classification Algorithm for Tiny Defects

Wafer inspection is a crucial step in the semiconductor manufacturing process. Accurate inspection of wafer defects is of great significance in ensuring chip quality, improving production efficiency, and reducing cost losses. Surface defects, such as pits and scratches, have a significant impact on...

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Main Authors: Ma, Can, Jie, Luyang, Yao, Yiming, Xu, Tong, Hu, Lilei
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Jie, Luyang
Yao, Yiming
Xu, Tong
Hu, Lilei
description Wafer inspection is a crucial step in the semiconductor manufacturing process. Accurate inspection of wafer defects is of great significance in ensuring chip quality, improving production efficiency, and reducing cost losses. Surface defects, such as pits and scratches, have a significant impact on chip yield during the intricate wafer manufacturing process. For further higher inspection capability, conventional semiconductor inspection methods are limited by optical imaging resolution and signal capture capabilities, resulting in low efficiency. Therefore, there is a need for a more efficient and high-performance automatic wafer defect inspection method in the semiconductor manufacturing industry. To address this challenge, a deep learning network for wafer defect classification that uses spatial attention block and residual structure is proposed. Moreover, as defects in wafer images only occupy a very small portion of the entire image scale, therefore, easily overlooked. Therefore, hot-spot mapping and denoising were carried out to effectively enhance the defect features in the wafer images. The proposed algorithm is evaluated by classifying defects in real wafer data collected by a home-developed optical system. The algorithm has demonstrated a comprehensive classification performance, even with a limited number of defect samples, surpassing other models.
doi_str_mv 10.1109/ICAIT59485.2023.10367417
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fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_10367417</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10367417</ieee_id><sourcerecordid>10367417</sourcerecordid><originalsourceid>FETCH-LOGICAL-i119t-d365702b2fd92f7a2a123e7d8201b995f3368d73592e33a3b7f2e5131b474a6d3</originalsourceid><addsrcrecordid>eNo1kM1Kw0AYRUdBsNS8gYt5gcTvJ5PJLEOsWiiIGHFZJsmMHUnTksymb69ouzqbw-FyhZAIGSKYh3VdrRtl8lJlBMQZAhc6R30lEqNNyQoYcyS4FgvSGlIsgG9FMs_fAMAEOaBeiLf3o43BDrKK0Y0xHEa5Gnd27FwvP613k3x03nVR1oOd5-BDZ_-kavg6TCHu9tIfJtmE8XQW5ztx4-0wu-TMpfh4WjX1S7p5ff7dvEkDoolpz4XSQC353pDXliwSO92XBNgaozxzUfaalSHHbLnVnpxCxjbXuS16Xor7_25wzm2PU9jb6bS9vMA_EXFQ5w</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Spatial Attention Enhanced Wafer Defect Classification Algorithm for Tiny Defects</title><source>IEEE Xplore All Conference Series</source><creator>Ma, Can ; Jie, Luyang ; Yao, Yiming ; Xu, Tong ; Hu, Lilei</creator><creatorcontrib>Ma, Can ; Jie, Luyang ; Yao, Yiming ; Xu, Tong ; Hu, Lilei</creatorcontrib><description>Wafer inspection is a crucial step in the semiconductor manufacturing process. Accurate inspection of wafer defects is of great significance in ensuring chip quality, improving production efficiency, and reducing cost losses. Surface defects, such as pits and scratches, have a significant impact on chip yield during the intricate wafer manufacturing process. For further higher inspection capability, conventional semiconductor inspection methods are limited by optical imaging resolution and signal capture capabilities, resulting in low efficiency. Therefore, there is a need for a more efficient and high-performance automatic wafer defect inspection method in the semiconductor manufacturing industry. To address this challenge, a deep learning network for wafer defect classification that uses spatial attention block and residual structure is proposed. Moreover, as defects in wafer images only occupy a very small portion of the entire image scale, therefore, easily overlooked. Therefore, hot-spot mapping and denoising were carried out to effectively enhance the defect features in the wafer images. The proposed algorithm is evaluated by classifying defects in real wafer data collected by a home-developed optical system. The algorithm has demonstrated a comprehensive classification performance, even with a limited number of defect samples, surpassing other models.</description><identifier>EISSN: 2770-1603</identifier><identifier>EISBN: 9798350314120</identifier><identifier>DOI: 10.1109/ICAIT59485.2023.10367417</identifier><language>eng</language><publisher>IEEE</publisher><subject>Classification algorithms ; Costs ; Deep learning ; defect classification ; Inspection ; Optical imaging ; Semiconductor device manufacture ; Semiconductor device modeling ; semiconductor inspection ; spatial attention</subject><ispartof>2023 IEEE 15th International Conference on Advanced Infocomm Technology (ICAIT), 2023, p.380-384</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10367417$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10367417$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ma, Can</creatorcontrib><creatorcontrib>Jie, Luyang</creatorcontrib><creatorcontrib>Yao, Yiming</creatorcontrib><creatorcontrib>Xu, Tong</creatorcontrib><creatorcontrib>Hu, Lilei</creatorcontrib><title>Spatial Attention Enhanced Wafer Defect Classification Algorithm for Tiny Defects</title><title>2023 IEEE 15th International Conference on Advanced Infocomm Technology (ICAIT)</title><addtitle>ICAIT</addtitle><description>Wafer inspection is a crucial step in the semiconductor manufacturing process. Accurate inspection of wafer defects is of great significance in ensuring chip quality, improving production efficiency, and reducing cost losses. Surface defects, such as pits and scratches, have a significant impact on chip yield during the intricate wafer manufacturing process. For further higher inspection capability, conventional semiconductor inspection methods are limited by optical imaging resolution and signal capture capabilities, resulting in low efficiency. Therefore, there is a need for a more efficient and high-performance automatic wafer defect inspection method in the semiconductor manufacturing industry. To address this challenge, a deep learning network for wafer defect classification that uses spatial attention block and residual structure is proposed. Moreover, as defects in wafer images only occupy a very small portion of the entire image scale, therefore, easily overlooked. Therefore, hot-spot mapping and denoising were carried out to effectively enhance the defect features in the wafer images. The proposed algorithm is evaluated by classifying defects in real wafer data collected by a home-developed optical system. The algorithm has demonstrated a comprehensive classification performance, even with a limited number of defect samples, surpassing other models.</description><subject>Classification algorithms</subject><subject>Costs</subject><subject>Deep learning</subject><subject>defect classification</subject><subject>Inspection</subject><subject>Optical imaging</subject><subject>Semiconductor device manufacture</subject><subject>Semiconductor device modeling</subject><subject>semiconductor inspection</subject><subject>spatial attention</subject><issn>2770-1603</issn><isbn>9798350314120</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2023</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1kM1Kw0AYRUdBsNS8gYt5gcTvJ5PJLEOsWiiIGHFZJsmMHUnTksymb69ouzqbw-FyhZAIGSKYh3VdrRtl8lJlBMQZAhc6R30lEqNNyQoYcyS4FgvSGlIsgG9FMs_fAMAEOaBeiLf3o43BDrKK0Y0xHEa5Gnd27FwvP613k3x03nVR1oOd5-BDZ_-kavg6TCHu9tIfJtmE8XQW5ztx4-0wu-TMpfh4WjX1S7p5ff7dvEkDoolpz4XSQC353pDXliwSO92XBNgaozxzUfaalSHHbLnVnpxCxjbXuS16Xor7_25wzm2PU9jb6bS9vMA_EXFQ5w</recordid><startdate>20231013</startdate><enddate>20231013</enddate><creator>Ma, Can</creator><creator>Jie, Luyang</creator><creator>Yao, Yiming</creator><creator>Xu, Tong</creator><creator>Hu, Lilei</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20231013</creationdate><title>Spatial Attention Enhanced Wafer Defect Classification Algorithm for Tiny Defects</title><author>Ma, Can ; Jie, Luyang ; Yao, Yiming ; Xu, Tong ; Hu, Lilei</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i119t-d365702b2fd92f7a2a123e7d8201b995f3368d73592e33a3b7f2e5131b474a6d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Classification algorithms</topic><topic>Costs</topic><topic>Deep learning</topic><topic>defect classification</topic><topic>Inspection</topic><topic>Optical imaging</topic><topic>Semiconductor device manufacture</topic><topic>Semiconductor device modeling</topic><topic>semiconductor inspection</topic><topic>spatial attention</topic><toplevel>online_resources</toplevel><creatorcontrib>Ma, Can</creatorcontrib><creatorcontrib>Jie, Luyang</creatorcontrib><creatorcontrib>Yao, Yiming</creatorcontrib><creatorcontrib>Xu, Tong</creatorcontrib><creatorcontrib>Hu, Lilei</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ma, Can</au><au>Jie, Luyang</au><au>Yao, Yiming</au><au>Xu, Tong</au><au>Hu, Lilei</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Spatial Attention Enhanced Wafer Defect Classification Algorithm for Tiny Defects</atitle><btitle>2023 IEEE 15th International Conference on Advanced Infocomm Technology (ICAIT)</btitle><stitle>ICAIT</stitle><date>2023-10-13</date><risdate>2023</risdate><spage>380</spage><epage>384</epage><pages>380-384</pages><eissn>2770-1603</eissn><eisbn>9798350314120</eisbn><abstract>Wafer inspection is a crucial step in the semiconductor manufacturing process. Accurate inspection of wafer defects is of great significance in ensuring chip quality, improving production efficiency, and reducing cost losses. Surface defects, such as pits and scratches, have a significant impact on chip yield during the intricate wafer manufacturing process. For further higher inspection capability, conventional semiconductor inspection methods are limited by optical imaging resolution and signal capture capabilities, resulting in low efficiency. Therefore, there is a need for a more efficient and high-performance automatic wafer defect inspection method in the semiconductor manufacturing industry. To address this challenge, a deep learning network for wafer defect classification that uses spatial attention block and residual structure is proposed. Moreover, as defects in wafer images only occupy a very small portion of the entire image scale, therefore, easily overlooked. Therefore, hot-spot mapping and denoising were carried out to effectively enhance the defect features in the wafer images. The proposed algorithm is evaluated by classifying defects in real wafer data collected by a home-developed optical system. The algorithm has demonstrated a comprehensive classification performance, even with a limited number of defect samples, surpassing other models.</abstract><pub>IEEE</pub><doi>10.1109/ICAIT59485.2023.10367417</doi><tpages>5</tpages></addata></record>
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subjects Classification algorithms
Costs
Deep learning
defect classification
Inspection
Optical imaging
Semiconductor device manufacture
Semiconductor device modeling
semiconductor inspection
spatial attention
title Spatial Attention Enhanced Wafer Defect Classification Algorithm for Tiny Defects
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T18%3A40%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Spatial%20Attention%20Enhanced%20Wafer%20Defect%20Classification%20Algorithm%20for%20Tiny%20Defects&rft.btitle=2023%20IEEE%2015th%20International%20Conference%20on%20Advanced%20Infocomm%20Technology%20(ICAIT)&rft.au=Ma,%20Can&rft.date=2023-10-13&rft.spage=380&rft.epage=384&rft.pages=380-384&rft.eissn=2770-1603&rft_id=info:doi/10.1109/ICAIT59485.2023.10367417&rft.eisbn=9798350314120&rft_dat=%3Cieee_CHZPO%3E10367417%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i119t-d365702b2fd92f7a2a123e7d8201b995f3368d73592e33a3b7f2e5131b474a6d3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=10367417&rfr_iscdi=true