A 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp

• Published in: IEEE journal of solid-state circuits 2024-07, Vol.59 (7), p.2209-2218
• Main Authors: Zhan, Mingtao, Jie, Lu, Tang, Xiyuan, Zhong, Yi, Sun, Nan
• Format: Article
• Language: English
• Subjects: Analog to digital converters; Analog-to-digital converter (ADC); Bandwidth; Cancellation; Capacitance; Capacitors; Figure of merit; kT/C noise cancellation; Noise cancellation; pipeline; Pipelines; Power consumption; Registers; ring amplifier (ring-amp); ringamp; Robustness; Sampling; successive-approximation register (SAR); Sun; Switches; Thermal noise
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2023.3344461

This article presents a compact 13-bit 200-MS/s pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) with a robust current-biased ring amplifier (ring-amp) and kT/C noise cancellation. The proposed current-biasing scheme using split capacitors significantly enhances the PVT robustness of the ring-amp. With additional split capacitors used for current-biasing, the kT/C noise cancellation technique can be seamlessly implemented in this architecture. With kT/C noise cancellation, the input-referred thermal noise can break the input sampling kT/C noise limit. As a result, the input sampling capacitance can be greatly reduced. With only 128-fF single-end input sampling capacitance, the prototype ADC implemented in a 28-nm process achieves 67-dB SNDR with only 0.004-mm2 core area. The power consumption at 200 MS/s is 1.3 mW, yielding a Schreier figure of merit of 175.5 dB and a Walden figure of merit of 3.7 fJ/conversion-step.