Simultaneous Spike Processing for 3D NAND-Based Spiking Neural Networks

Compute-in-Memory (CiM) with high bit density is crucial for implementing large-scale neural networks, and the CiM based on a three-dimensional (3D) NAND can be a strong candidate for this purpose. In the conventional 3D NAND CiM, the weight mapping strategy allocates synaptic layers to the correspo...

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Bibliographic Details
Published in:IEEE electron device letters 2024-03, Vol.45 (3), p.340-343
Main Authors: Jeon, Bosung, Song, Seunghwan, Kim, Jae-Joon, Choi, Woo Young
Format: Article
Language:English
Subjects:
3D NAND-based compute-in-memory (CiM)
Charge trap flash (CTF)
Flash memories
In-memory computing
Mapping
Memory architecture
Multilayers
Network latency
Neural networks
Neurons
spiking neural network (SNN)
Spiking neural networks
Three-dimensional displays
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Summary:Compute-in-Memory (CiM) with high bit density is crucial for implementing large-scale neural networks, and the CiM based on a three-dimensional (3D) NAND can be a strong candidate for this purpose. In the conventional 3D NAND CiM, the weight mapping strategy allocates synaptic layers to the corresponding word lines. This approach induces sequential spike processing across neural network layers and is not compatible with spiking neural networks (SNNs). To overcome this issue, we propose a novel weight mapping method that enables inter-layer simultaneous spike processing in the 3D NAND by mapping the synaptic layers to their corresponding bit lines. We experimentally validated the functionality of the proposed method using a specialized control scheme and the fabricated NAND arrays. In addition, a system-level simulation of a multi-layer SNN processing using our mapping technique demonstrates a substantial reduction in inference latency, increased robustness to synaptic cell variations, and over a 76.3x improvement in computing efficiency.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2024.3355889