Enhanced Endurance Characteristics in High Performance 16nm Selector Only Memory (SOM)

• Main Authors: Park, I.-M., Lee, K. W., Park, J.-H., Song, S. J., Kim, T. Y., Wu, Z., Lee, W. J., Choi, B. D., Jeong, Y. J., Oh, S. C., Park, K., Kuh, B. J., Song, Y. J., Shin, Y. G., Song, J. H.
• Format: Conference Proceeding
• Language: English
• Subjects: Current measurement; Energy measurement; Optimization; Performance evaluation; Pulse measurements; Size measurement
• ISSN: 2156-017X
• DOI: 10.1109/IEDM45741.2023.10413748

It has been successfully achieved the memory characteristics of a 64Gb array in a single ovonic threshold switch (OTS)-based selector only memory (SOM) with a size of 16nm. We have verified a read window margin (RWM) of 0.5 V, effectively operating at speeds below 56ns and with an applied current of 40μΑ. Particularly, the RWM remains consistently stable even variations in size of the OTS ranging from 15nm to 25nm, providing an advantage for scaling down and offering favorable memory characteristics. However, in SOMs, it remains challenging to maintain the original characteristics of the OTS when external elements penetrate, and the presence of spike current (I S ) during turn-on renders the SOM vulnerable in terms of endurance. To address these challenges, we implemented processes aimed at minimizing process-induced damage (PID) to the OTS and optimized the configuration of the cell stack to mitigate the impact of I S . Consequently, we achieved stable write endurance for up to 10 8 cycles and read endurance exceeding 10 9 cycles.