Test methodology for Motorola's high performance e500 core based on PowerPC instruction set architecture

This paper presents the DFT techniques used in Motorola's high performance e500 core, which implements the PowerPC "Book E" architecture and is designed to run at 600 MHz to 1 GHz. Highlights of the DFT features are at-speed logic built-in self-test (LBIST) for delay fault detection,...

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Bibliographic Details
Main Authors: Bailey, B., Metayer, A., Svrcek, B., Tendolkar, N., Wolf, E., Fiene, E., Alexander, M., Woltenberg, R., Raina, R.
Format: Conference Proceeding
Language:English
Subjects:
Applied sciences
Automatic testing
Built-in self-test
Delay
Design for testability
Electronics
Exact sciences and technology
Frequency
Integrated circuits
Integrated circuits by function (including memories and processors)
Logic arrays
Logic design
Logic testing
Magnetic and optical mass memories
Microelectronic fabrication (materials and surfaces technology)
Microprocessors
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Storage and reproduction of information
Testing, measurement, noise and reliability
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Summary:This paper presents the DFT techniques used in Motorola's high performance e500 core, which implements the PowerPC "Book E" architecture and is designed to run at 600 MHz to 1 GHz. Highlights of the DFT features are at-speed logic built-in self-test (LBIST) for delay fault detection, very high test coverage for scan based at-speed deterministic delay-fault test patterns, 100% BIST for embedded memory arrays and 99.2 % stuck-at fault test coverage for deterministic scan test patterns. A salient design feature is the isolation ring that facilitates testing of the core when it is integrated in an SoC or host processor.
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2002.1041808