Pipelined CORDIC Architecture Based DDFS Design and Implementation

• Main Authors: Verma, Sandeep Kumar, Pullakandam, Muralidhar, Yanamala, Rama Muni Reddy
• Format: Conference Proceeding
• Language: English
• Subjects: Computer architecture; CORDIC; DDFS; FPGA; Hardware implementation; ILA; Pipeline; Pipelines; Power demand; Resource management; Signal processing algorithms; Simulation; Synthetic aperture radar; Table lookup; Verilog HDL; VIO
• ISSN: 2325-9418
• DOI: 10.1109/INDICON59947.2023.10440811

In this paper, an efficient approach is presented to design and implement a moderate speed and area efficient digital sinusoidal and cosinusoidal wave generator for wireless applications like RADAR, Digital Signal Processing. The implementation is based on direct digital frequency synthesizer using Coordinate Rotation Digital Computer (CORDIC) algorithm which uses shifts, additions, and a very small look-up table (LUT). It is an efficient method used to compute trigonometric functions, multiplications, divisions, data type conversions, and hyperbolic functions simply and elegantly. The proposed design is synthesized with Xilinx Vivado v.2022.2 tools, simulated with Vivado Built-in simulator, and practically verified the designed CORDIC processor IP with Virtual Input Output (VIO), and Integrated Logic Analyzer (ILA) on Xilinx NEXYS 4 DDR (XC7A100T-CSG324) Artix-7 Series FPGA Board. The project attempts to reduce resource use while enhancing delay, accuracy, resolution, and area. The results demonstrated improved performance using the proposed CORDIC algorithm in terms of power consumption, high resolution, resource utilization, and generate moderate speed of sinusoidal and cosine waveforms for a frequency range from 2.78 x 10 -5 MHz to 99.72 MHz.