13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry

• Main Authors: Yang, Jaehyeok, Ko, Hyeongjun, Kim, Kyunghoon, Park, Hyunsu, Park, Jihwan, Kang, Ji-Hyo, Cha, Jinyoup, Kim, Seongjin, Kim, Youngtaek, Park, Minsoo, Lee, Gangsik, Lee, Keonho, Lee, Sanghoon, Jeon, Gyunam, Jeong, Sera, Joo, Yongsuk, Cha, Jaehoon, Hwang, Seonwoo, Kim, Boram, Byeon, Sangyeon, Lee, Sungkwon, Park, Hyeonyeol, Cho, Joohwan, Kim, Jonghwan
• Format: Conference Proceeding
• Language: English
• Subjects: Bandwidth; Graphics; Power demand; Reliability; SDRAM; Solid state circuits; Streaming media
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC49657.2024.10454560

The increase in GPU-based AI applications, cloud-based gaming, and video streaming services has driven the need for new a graphics memory that operates at higher bandwidth and power efficiency than existing GDDR6 SDRAM, leading to the introduction of the GDDR7 standard [1]. Since performance degradation due to thermal throttling, power cost, and device reliability are major development considerations in high-power graphics applications, PAM3 signaling is applied on single-ended pins to improve bandwidth and power consumption, while maintaining the clock frequency [2]. However, new PAM3-related blocks supporting double the bandwidth inevitably increase in absolute power and temperature. In this paper, we present additional power reduction techniques, while maintaining SNR. The clocking architecture, with fast wake-up capabilities, can be partially disabled to provide active-standby current (IDD3N) as low as the power-down mode. The PAM3 TX and RX use a design approach that achieves high SNR and power efficiency.