Highly Linear Charging/Discharging of Charge Trap FET Using Regulated Single Pulse for Neural Accelerator

• Main Authors: Choi, Jeong-In, Lee, Seo-Yoon, Park, Chan-Woong, Oh, Jin-Gon, Kang, Ji Hoon, Kwon, Kee-Won
• Format: Conference Proceeding
• Language: English
• Subjects: Charge-trap FET(CTF); Field effect transistors; In-memory-computing(IMC); Interference; ISPP; Linearity; Non-volatile memory(NVM); Nonvolatile memory; Programming; Virtual machine monitors; Writing
• ISSN: 2767-7699
• DOI: 10.1109/ICEIC61013.2024.10457242

In the realm of artificial neural network implementation, where vast data handling is imperative, In-Memory Computing (IMC) technology is emerging to mitigate data bottlenecks in current memory architectures. Synaptic cells based on Single Poly Floating Gate FET (FGF) exhibit exceptional linearity between input voltage and output current, capitalizing on capacitive coupling via drain capacitance. Consequently, researchers have explored single poly FGF-based vector matrix multipliers (VMM). However, with escalating computational requirements, FGF, which confines charges in conductors, confronts limitations concerning cell interference. This interference is critical for achieving area efficiency in neural network IC design, and FGF tends to occupy a substantial charge storage area. On the other hand, Charge Trap FET (CTF), which stores charges in the insulator, offers a superior degree of interference resistance among cells compared to FGF. It is also advantageous in terms of area efficiency. Nevertheless, CTF grapples with suboptimal linearity between input and output due to its incapacity to control capacitance. Thus, in this paper, we propose a method for linearly writing in CTF cells for vector matrix multiplication based on ISPP. Through the application of ISPP to CTF in this study, it was confirmed that a linearity improvement of 4.2% to 4.8% in PGM can be achieved compared to CPP.