Address Scaling: Architectural Support for Fine-Grained Thread-Safe Metadata Management

• Published in: IEEE computer architecture letters 2024-01, Vol.23 (1), p.1-4
• Main Authors: Mishra, Deepanjali, Kanellopoulos, Konstantinos, Panwar, Ashish, Sriraman, Akshitha, Seshadri, Vivek, Mutlu, Onur, Mowry, Todd C.
• Format: Article
• Language: English
• Subjects: Data management; dynamic program monitoring tools; Intermediate address space; Metadata; metadata management; Monitoring; Performance enhancement; Precipitates; Run time (computers); Scaling; virtual memory
• ISSN: 1556-6056; 1556-6064
• DOI: 10.1109/LCA.2024.3373760

In recent decades, software systems have grown significantly in size and complexity. As a result, such systems are more prone to bugs which can cause performance and correctness challenges. Using run-time monitoring tools is one approach to mitigate these challenges. However, these tools maintain metadata for every byte of application data they monitor, which precipitates performance overheads from additional metadata accesses. We propose Address Scaling , a new hardware framework that performs fine-grained metadata management to reduce metadata access overheads in run-time monitoring tools. Our mechanism is based on the observation that different run-time monitoring tools maintain metadata at varied granularities. Our key insight is to maintain the data and its corresponding metadata within the same cache line, to preserve locality. Address Scaling improves the performance of Memcheck , a dynamic monitoring tool that detects memory-related errors, by 3.55× and 6.58× for sequential and random memory access patterns respectively, compared to the state-of-the-art systems that store the metadata in a memory region that is separate from the data.