On Decomposing Complex Test Cases for Efficient Post-Silicon Validation

• Main Authors: C, Harshitha, Harikrishna, Sundarapalli, Rohith, Peddakotla, Chandran, Sandeep, Kalayappan, Rajshekar
• Format: Conference Proceeding
• Language: English
• Subjects: Asia; Benchmark testing; Debugging; Design automation; Hardware; Hardware > Hardware test; Hardware > Hardware validation; Hardware > Hardware validation > Functional verification; Hardware > Robustness; Intellectual property; Silicon; Source coding
• ISSN: 2153-697X
• DOI: 10.1109/ASP-DAC58780.2024.10473813

In post-silicon validation, the first step when an erroneous behavior is uncovered by a long-running test case is to reproduce the observed behavior in a shorter execution. This makes it amenable to use a variety of tools and techniques to debug the error. In this work, we propose a tool called Gru, that takes a long execution trace as input and generates a set of executables, one for each section of the trace. Each generated executable is guaranteed to faithfully replicate the behavior observed in the corresponding section of the original, complex test case independently. This enables the generated executables to be run simultaneously across different silicon samples, thereby allowing further debugging activities to proceed in parallel. The generation of executables does not require the source code of the complex test case and hence supports privacy-aware debugging in scenarios involving sensitive Intellectual Properties (IPs). We demonstrate the effectiveness of this tool on a collection of 10 EEMBC benchmarks that are executed on a bare-metal LEON3 SoC.