A High Throughput ASCON Architecture for Secure Edge IoT Devices

ASCON is a LightWeight Cryptographic (LWC) algorithm that has been selected by NIST as the standard in resource-constrained environments like the Internet of Things (IoT). ASCON is a well-secured implementation that requires low-power, low computational resources because of its efficient and simple...

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Bibliographic Details
Main Authors: Koppuravuri, Ayyappa, Pasupuleti, Haribabu, Gvk, Sasirekha, Bapat, Jyotsna
Format: Conference Proceeding
Language:English
Subjects:
AEAD
ASCON
Computer architecture
Hardware
Image edge detection
IoMT devices
IoT security
lightweight cryptography
LTE
NIST
Streaming media
Surveys
Throughput
Very large scale integration
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Description
Summary:ASCON is a LightWeight Cryptographic (LWC) algorithm that has been selected by NIST as the standard in resource-constrained environments like the Internet of Things (IoT). ASCON is a well-secured implementation that requires low-power, low computational resources because of its efficient and simple architecture. The literature survey shows several FPGA implementations of ASCON. In this paper, we propose a novel integrated architecture for the hardware implementation of ASCON by which higher throughput can be realized. The synthesis results have been generated across various FPGA boards from Xilinx, like Artix-7 Nexys4, Virtex-7, and Spartan-6, which show an increase in throughput up to 31.77% with an increase in throughput per area up to 89.51% when compared to the previous implementations for the ASCON-128. A throughput of 729 Mbps has been observed on the Virtex-7 FPGA board. Such a throughput would be ideal for real-time medical images and video transfer while supporting LWC for IoT edge devices.
ISSN:2380-6923
DOI:10.1109/VLSID60093.2024.00087