3D FO package technology using bridge die for high number of chiplets integration

• Main Authors: Zhuang, Jiaming, Li, Shangxuan, Zhang, Xc, Chen, Ivan, Chen, Bruce, Hsieh, Simon, Yang, Bohan, Chung, C. Key, Xia, Xin
• Format: Conference Proceeding
• Language: English
• Subjects: 3D stacking packaging; Bridge circuits; Bridges; Chip first; Chip last; Costs; FOED; HPC; Packaging; Si bridge die; Stacking; Three-dimensional displays; Through mold via; Wiring
• ISSN: 2836-9823
• DOI: 10.1109/ICEPT59018.2023.10492294

Moore's Law has been reaching its physical limits, while high-performance computing (HPC) market continues to demand for faster processing speeds, lower latency, and higher bandwidth. Many IC designers have disintegrated the functions of the dies into several smaller dies for lower cost, and higher performances. These smaller dies are named as chiplets that will be integrated together via assembly packaging.Since TSMC has been successfully developed 2.5D for Xilinx in 2014; 2.5D package has been overwhelming for the HPC purposes. As it able to integrate multi chiplets into a single module. But, as we pack higher number of chiplets, the size of the module is getting bigger. Accordingly, the residue stress is growing due to CTE (coefficient of thermal expansion) mismatch between Through Si Interposer (TSI) and organic substrate. Besides, the number of TSI per wafer is getting lesser. And higher cost is incurred. Additionally, TSI has its parasitic capacitance. This phenomenon is in particularly significant as the processing speed is growing beyond 4 GHz [1].To overcome the 2.5D limitations, in this paper, we have successfully developed a new type of fan-out technology using high-density wiring of Si bridge die to replace the TSI. We validated this packaging technology with one SOC and two I/O dies (IOD). Instead of using TSI, we replace this with Si bridge die. The size of the bridge dies is 6.7 x 5.2 mm2; dies per wafer are 1804 pieces. As compared to 2.5D with similar package, the TSI per wafer are only 66 pieces. Based on 2 bridge dies are used to connect between SOC and IOD, we have increased the die capacity by 13 times. With that reason, the package costs have been improved significantly. This new type of package is named as Fan-Out Embedded Die (FOED). And the package has been developed earlier but with different approaches [2], [3]. And the final package is developed. Since the die to package ratio is low, and the CTE is well matched to the organic substrate, thus, the performance of reliability is better. Details of the process and reliability performances of the package will be discussed in this paper.