Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers

Over the past few years, silent data corruption (SDC) has garnered significant attention. Some features of SDC, like intermittency and aging, are commonly encountered in the VLSI front-end-of-line (FEOL) reliability domain and are linked to FET gate oxide defects. In this work, we draw on these para...

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Bibliographic Details
Main Authors: Sangani, D., Kaczer, B., Weckx, P., Roussel, Ph. J., Mishra, S., Marinissen, E. J., Gielen, G.
Format: Conference Proceeding
Language:English
Subjects:
Aging
Circuit aging
Circuit faults
corrupt execution errors (CEE)
Logic gates
Noise
Probability
Silent data corruption (SDC)
Statistical analysis
Very large scale integration
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Summary:Over the past few years, silent data corruption (SDC) has garnered significant attention. Some features of SDC, like intermittency and aging, are commonly encountered in the VLSI front-end-of-line (FEOL) reliability domain and are linked to FET gate oxide defects. In this work, we draw on these parallels and use physical models of FEOL defects to define the main properties of an "archetypal" SDC fault. We then explain how such faults could be identified through their characteristic "signatures". We give examples of fault signatures related to gate-oxide breakdown (BD) and random telegraph noise (RTN). Furthermore, we propose a "prime and test" screening methodology for RTN-related faults. We also show that device variability will enhance the probability of SDC.
ISSN:1938-1891
DOI:10.1109/IRPS48228.2024.10529436