An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture

Adopting specialized accelerators such as Coarse-Grained Reconfigurable Architectures (CGRAs) alongside CPUs to enhance performance within specific domains is an astute choice. However, the integration of heterogeneous architectures introduces complex challenges for compiler design. Simultaneously,...

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Bibliographic Details
Main Authors: Lou, Jiahang, Gao, Xuchen, Mao, Yiqing, Qiu, Yunhui, Hu, Yihan, Yin, Wenbo, Wang, Lingli
Format: Conference Proceeding
Language:English
Subjects:
Automation
Bridges
CGRA
compiler
Computer architecture
Hardware
heterogeneous architecture
MLIR
Reconfigurable architectures
Scalability
Software
software-hardware partition
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Summary:Adopting specialized accelerators such as Coarse-Grained Reconfigurable Architectures (CGRAs) alongside CPUs to enhance performance within specific domains is an astute choice. However, the integration of heterogeneous architectures introduces complex challenges for compiler design. Simultaneously, the ever-expanding scale of workloads imposes substantial burdens on deployment. To address above challenges, this paper introduces CGRV-OPT, a user-friendly multi-level compiler designed to deploy large-scale workloads to CGRA and RISC-V CPU architecture. Built upon the MLIR framework, CGRV-OPT serves as a pivotal bridge, facilitating the seamless conversion of high-level workload descriptions into low-level intermediate representations (IRs) for different architectures. A salient feature of our approach is the automation of a comprehensive suite of optimizations and transformations, which speed up each kernel computing within the intricate SoC. Additionally, we have seamlessly integrated an automated software-hardware partitioning mechanism, guided by our multi-level optimizations, resulting in a remarkable 2.14 × speed up over large-scale workloads. The CGRV-OPT framework significantly alleviates the challenges faced by software developers, including those with limited expertise in hardware architectures.
ISSN:1558-1101
DOI:10.23919/DATE58400.2024.10546646