Constrained Sorter Design using Zero-One Principle

To derive efficient sorting architectures constrained to application-specific input/output conditions, we present in this paper a systematic design methodology that can effectively prune dispensable compare-and-swap (CAS) units. Unlike the previous works resorting to heuristic approaches, the propos...

Full description

Saved in:
Bibliographic Details
Main Authors: Han, Sangil, Kim, Jaehee, Kam, Dongyun, Kong, Byeong Yong, Kim, Mijung, Kim, Young-Seok, Lee, Youngjoo
Format: Conference Proceeding
Language:English
Subjects:
Circuits and systems
Complexity theory
Computer architecture
Decoding
Design methodology
Hardware
low-complexity architecture
Sorter
Systematics
VLSI design
zero-one principle
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:To derive efficient sorting architectures constrained to application-specific input/output conditions, we present in this paper a systematic design methodology that can effectively prune dispensable compare-and-swap (CAS) units. Unlike the previous works resorting to heuristic approaches, the proposed framework exploits the zero-one principle to validate the pruning of a CAS unit at a time, generating the cost-optimized sorter architecture in an iterative manner with a reasonable complexity. In addition to the given input/output constraints, we newly develop the architecture options for the proposed framework, allowing more design spaces for finding the most attractive constrained-sorter design. For 8-list polar decoders, the proposed framework successfully reduces 70% of CAS units in the baseline full sorter, relaxing the area-time complexity by 35% compared with the state-of-the-art solutions.
ISSN:2158-1525
DOI:10.1109/ISCAS58744.2024.10557942