A 27.5 fJ/step SAR Capacitance-to-Digital Converter Based on Correlated Double Sampling

This paper presents a low-power and energy-efficient capacitance-to-digital converter (CDC) for a single-end sensor based on correlated double sampling (CDS) technology. The CDS is accomplished by two opposite conversions, which reuse the comparator, C SENS , and C DAC . The proposed CDC eliminates...

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Bibliographic Details
Main Authors: Xia, Qingjiang, You, You, Zhang, Yacong, Lu, Wengao, Zhu, Runkun, Chen, Zhongjian
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Capacitance-to-digital converter (CDC)
Circuits
Correlated-double sampling (CDS)
Energy efficiency
Floating inverter-based amplifier (FIA)
Interference
Noise
Prototypes
Simulation
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Summary:This paper presents a low-power and energy-efficient capacitance-to-digital converter (CDC) for a single-end sensor based on correlated double sampling (CDS) technology. The CDS is accomplished by two opposite conversions, which reuse the comparator, C SENS , and C DAC . The proposed CDC eliminates the parasitic-dependent error caused by the comparator's offset without extra consumption through the CDS. The simulation results show that the CDC can eliminate low-frequency interference and achieve anti-common-mode interference capabilities similar to differential circuits. To achieve low noise and high energy efficiency, the CDC employs a floating inverter amplifier (FIA) as the pre-amplifier of the comparator. Implemented in a 0.18 μm CMOS process, it consumes 0.91 μW from a 1.2 V supply. The simulation results show an effective number of 11.69 bits and an energy efficiency of 27.5 fJ per conversion step.
ISSN:2158-1525
DOI:10.1109/ISCAS58744.2024.10558248